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Brent Kandetzki3f1a5c12010-03-24 17:41:33 -04001/*
2 * U-boot - Configuration file for IP04 board (having BF532 processor)
3 *
4 * Copyright (c) 2006 Intratrade Ltd., Ivan Danov, idanov@gmail.com
5 *
6 * Copyright (c) 2005-2010 Analog Devices Inc.
7 *
8 * (C) Copyright 2000-2004
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
10 *
11 * Licensed under the GPL-2 or later.
12 */
13
14#ifndef __CONFIG_IP04_H__
15#define __CONFIG_IP04_H__
16
17#include <asm/config-pre.h>
18
19
20/*
21 * Processor Settings
22 */
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -040023#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_NAND
24
25
26/*
27 * Clock Settings
28 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
29 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
30 */
31/* CONFIG_CLKIN_HZ is any value in Hz */
32#define CONFIG_CLKIN_HZ 10000000
33/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
34/* 1 = CLKIN / 2 */
35#define CONFIG_CLKIN_HALF 0
36/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
37/* 1 = bypass PLL */
38#define CONFIG_PLL_BYPASS 0
39/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
40/* Values can range from 0-63 (where 0 means 64) */
41#define CONFIG_VCO_MULT 40
42/* CCLK_DIV controls the core clock divider */
43/* Values can be 1, 2, 4, or 8 ONLY */
44#define CONFIG_CCLK_DIV 1
45/* SCLK_DIV controls the system clock divider */
46/* Values can range from 1-15 */
47#define CONFIG_SCLK_DIV 3
48
49
50/*
51 * Memory Settings
52 */
53#define CONFIG_MEM_ADD_WDTH 10
54#define CONFIG_MEM_SIZE 64
55
56#define CONFIG_EBIU_SDRRC_VAL 0x408
57#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
58
59#define CONFIG_EBIU_AMGCTL_VAL 0xFF
60#define CONFIG_EBIU_AMBCTL0_VAL 0xffc2ffc2
61#define CONFIG_EBIU_AMBCTL1_VAL 0xffc2ffc2
62
63#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
64#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
65
66
67/*
68 * Network Settings
69 */
70#define ADI_CMDS_NETWORK 1
71#define CONFIG_NET_MULTI 1
72#define CONFIG_HOSTNAME IP04
73
74#define CONFIG_DRIVER_DM9000 1
75#define CONFIG_DM9000_NO_SROM
76#define CONFIG_DM9000_BASE 0x20100000
77#define DM9000_IO CONFIG_DM9000_BASE
78#define DM9000_DATA (CONFIG_DM9000_BASE + 2)
79
80
81/*
82 * Flash Settings
83 */
84#define CONFIG_ENV_OVERWRITE 1
85#define CONFIG_SYS_NO_FLASH /* we have only NAND */
86
87
88/*
89 * SPI Settings
90 */
91#define CONFIG_BFIN_SPI
92#define CONFIG_ENV_SPI_MAX_HZ 30000000
93#define CONFIG_SF_DEFAULT_SPEED 30000000
94#define CONFIG_SPI_FLASH
95#define CONFIG_SPI_FLASH_STMICRO
96#define CONFIG_SPI_FLASH_WINBOND
97
98
99/*
100 * Env Storage Settings
101 */
102#define CONFIG_ENV_IS_IN_SPI_FLASH
103#define CONFIG_PREBOOT "echo starting from spi flash"
104#define CONFIG_ENV_OFFSET 0x30000
105#define CONFIG_ENV_SIZE 0x10000
106#define CONFIG_ENV_SECT_SIZE 0x10000
107
108
109/*
110 * NAND Settings
111 */
112#define CONFIG_NAND_PLAT
113#define CONFIG_SYS_NAND_BASE 0x20000000
114#define CONFIG_SYS_MAX_NAND_DEVICE 1
115
116#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
117#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400118#define BFIN_NAND_WRITE(addr, cmd) \
119 do { \
120 bfin_write8(addr, cmd); \
121 SSYNC(); \
122 } while (0)
123
124#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
125#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
Mike Frysinger67ceefa2010-07-05 04:55:05 -0400126#define NAND_PLAT_GPIO_DEV_READY GPIO_PF10
Brent Kandetzki3f1a5c12010-03-24 17:41:33 -0400127
128
129/*
130 * Misc Settings
131 */
132#define CONFIG_BAUDRATE 115200
133#define CONFIG_MISC_INIT_R /* needed for MAC address */
134#define CONFIG_UART_CONSOLE 0
135
136#undef CONFIG_SHOW_BOOT_PROGRESS
137/* Enable this if bootretry required; currently it's disabled */
138#define CONFIG_BOOT_RETRY_TIME -1
139#define CONFIG_BOOTCOMMAND "run nandboot"
140#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
141
142
143/*
144 * Pull in common ADI header for remaining command/environment setup
145 */
146#include <configs/bfin_adi_common.h>
147
148#endif