blob: da16726d868cbcd6050bd169fc7a1d624b1bc2d8 [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01001/*
Aubrey.Li3f0606a2007-03-09 13:38:44 +08002 * U-boot - u-boot.lds.S
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01003 *
Mike Frysinger9171fc82008-03-30 15:46:13 -04004 * Copyright (c) 2005-2008 Analog Device Inc.
Wolfgang Denk6cb142f2006-03-12 02:12:27 +01005 *
6 * (C) Copyright 2000-2004
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Aubrey.Li3f0606a2007-03-09 13:38:44 +080028#include <config.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -040029#include <asm/blackfin.h>
30#undef ALIGN
Mike Frysingerb9eecc32008-10-24 17:48:54 -040031#undef ENTRY
32#undef bfin
Mike Frysinger9171fc82008-03-30 15:46:13 -040033
34/* If we don't actually load anything into L1 data, this will avoid
35 * a syntax error. If we do actually load something into L1 data,
36 * we'll get a linker memory load error (which is what we'd want).
37 * This is here in the first place so we can quickly test building
38 * for different CPU's which may lack non-cache L1 data.
39 */
40#ifndef L1_DATA_B_SRAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define L1_DATA_B_SRAM CONFIG_SYS_MONITOR_BASE
Mike Frysinger9171fc82008-03-30 15:46:13 -040042# define L1_DATA_B_SRAM_SIZE 0
43#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +080044
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010045OUTPUT_ARCH(bfin)
Mike Frysinger9171fc82008-03-30 15:46:13 -040046
47/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
48MEMORY
49{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050 ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
Mike Frysinger9171fc82008-03-30 15:46:13 -040051 l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
52 l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
53}
54
Mike Frysingerb9eecc32008-10-24 17:48:54 -040055ENTRY(_start)
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010056SECTIONS
57{
Mike Frysinger9171fc82008-03-30 15:46:13 -040058 .text :
59 {
Mike Frysingerb9eecc32008-10-24 17:48:54 -040060 cpu/blackfin/start.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040061
Mike Frysinger9171fc82008-03-30 15:46:13 -040062#ifdef ENV_IS_EMBEDDED
63 /* WARNING - the following is hand-optimized to fit within
64 * the sector before the environment sector. If it throws
65 * an error during compilation remove an object here to get
66 * it linked after the configuration sector.
67 */
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010068
Mike Frysingerb9eecc32008-10-24 17:48:54 -040069 cpu/blackfin/traps.o (.text .text.*)
70 cpu/blackfin/interrupt.o (.text .text.*)
71 cpu/blackfin/serial.o (.text .text.*)
72 common/dlmalloc.o (.text .text.*)
73 lib_generic/crc32.o (.text .text.*)
74 lib_generic/zlib.o (.text .text.*)
75 board/bf533-ezkit/bf533-ezkit.o (.text .text.*)
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010076
Mike Frysinger9171fc82008-03-30 15:46:13 -040077 . = DEFINED(env_offset) ? env_offset : .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040078 common/env_embedded.o (.text .text.*)
Mike Frysinger9171fc82008-03-30 15:46:13 -040079#endif
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010080
Mike Frysingerc23bff62008-10-11 20:47:58 -040081 __initcode_start = .;
Mike Frysingerb9eecc32008-10-24 17:48:54 -040082 cpu/blackfin/initcode.o (.text .text.*)
Mike Frysingerc23bff62008-10-11 20:47:58 -040083 __initcode_end = .;
84
Mike Frysinger9171fc82008-03-30 15:46:13 -040085 *(.text .text.*)
86 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010087
Mike Frysinger9171fc82008-03-30 15:46:13 -040088 .rodata :
89 {
90 . = ALIGN(4);
91 *(.rodata .rodata.*)
92 *(.rodata1)
93 *(.eh_frame)
94 . = ALIGN(4);
95 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +010096
Mike Frysinger9171fc82008-03-30 15:46:13 -040097 .data :
98 {
99 . = ALIGN(256);
100 *(.data .data.*)
101 *(.data1)
102 *(.sdata)
103 *(.sdata2)
104 *(.dynamic)
105 CONSTRUCTORS
106 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100107
Mike Frysinger9171fc82008-03-30 15:46:13 -0400108 .u_boot_cmd :
109 {
110 ___u_boot_cmd_start = .;
111 *(.u_boot_cmd)
112 ___u_boot_cmd_end = .;
113 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100114
Mike Frysinger9171fc82008-03-30 15:46:13 -0400115 .text_l1 :
116 {
117 . = ALIGN(4);
118 __stext_l1 = .;
119 *(.l1.text)
120 . = ALIGN(4);
121 __etext_l1 = .;
122 } >l1_code AT>ram
123 __stext_l1_lma = LOADADDR(.text_l1);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100124
Mike Frysinger9171fc82008-03-30 15:46:13 -0400125 .data_l1 :
126 {
127 . = ALIGN(4);
128 __sdata_l1 = .;
129 *(.l1.data)
130 *(.l1.bss)
131 . = ALIGN(4);
132 __edata_l1 = .;
133 } >l1_data AT>ram
134 __sdata_l1_lma = LOADADDR(.data_l1);
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100135
Mike Frysinger9171fc82008-03-30 15:46:13 -0400136 .bss :
137 {
138 . = ALIGN(4);
139 __bss_start = .;
140 *(.sbss) *(.scommon)
141 *(.dynbss)
142 *(.bss .bss.*)
143 *(COMMON)
144 __bss_end = .;
145 } >ram
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100146}