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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
5 * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
6 *
7 * Modified for the TRAB board by
wdenkb0639ca2003-09-17 22:48:07 +00008 * (C) Copyright 2002-2003
Detlev Zundel792a09e2009-05-13 10:54:10 +02009 * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
wdenkfe8c2802002-11-03 00:38:21 +000010 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
wdenkfe8c2802002-11-03 00:38:21 +000031#include <config.h>
32#include <version.h>
33
34
35/* some parameters for the board */
36
37/*
38 *
39 * Copied from linux/arch/arm/boot/compressed/head-s3c2400.S
40 *
41 * Copyright (C) 2001 Samsung Electronics by chc, 010406
42 *
43 * TRAB specific tweaks.
44 *
45 */
46
47/* memory controller */
48#define BWSCON 0x14000000
49
50/* Bank0 */
wdenkb4757ce2003-11-17 21:45:27 +000051#define B0_Tacs 0x1 /* 1 clk */
52#define B0_Tcos 0x1 /* 1 clk */
53#define B0_Tacc 0x5 /* 8 clk */
54#define B0_Tcoh 0x1 /* 1 clk */
55#define B0_Tah 0x1 /* 1 clk */
wdenkfe8c2802002-11-03 00:38:21 +000056#define B0_Tacp 0x0
57#define B0_PMC 0x0 /* normal */
58
59/* Bank1 - SRAM */
wdenkb4757ce2003-11-17 21:45:27 +000060#define B1_Tacs 0x1 /* 1 clk */
61#define B1_Tcos 0x1 /* 1 clk */
62#define B1_Tacc 0x5 /* 8 clk */
63#define B1_Tcoh 0x1 /* 1 clk */
64#define B1_Tah 0x1 /* 1 clk */
wdenkfe8c2802002-11-03 00:38:21 +000065#define B1_Tacp 0x0
66#define B1_PMC 0x0 /* normal */
67
68/* Bank2 - CPLD */
wdenkb4757ce2003-11-17 21:45:27 +000069#define B2_Tacs 0x1 /* 1 clk */
70#define B2_Tcos 0x1 /* 1 clk */
71#define B2_Tacc 0x5 /* 8 clk */
72#define B2_Tcoh 0x1 /* 1 clk */
73#define B2_Tah 0x1 /* 1 clk */
wdenkfe8c2802002-11-03 00:38:21 +000074#define B2_Tacp 0x0
75#define B2_PMC 0x0 /* normal */
76
77/* Bank3 - setup for the cs8900 */
78#define B3_Tacs 0x3 /* 4 clk */
79#define B3_Tcos 0x3 /* 4 clk */
80#define B3_Tacc 0x7 /* 14 clk */
81#define B3_Tcoh 0x1 /* 1 clk */
82#define B3_Tah 0x0 /* 0 clk */
83#define B3_Tacp 0x3 /* 6 clk */
84#define B3_PMC 0x0 /* normal */
85
86/* Bank4 */
87#define B4_Tacs 0x0 /* 0 clk */
88#define B4_Tcos 0x0 /* 0 clk */
89#define B4_Tacc 0x7 /* 14 clk */
90#define B4_Tcoh 0x0 /* 0 clk */
91#define B4_Tah 0x0 /* 0 clk */
92#define B4_Tacp 0x0
93#define B4_PMC 0x0 /* normal */
94
95/* Bank5 */
96#define B5_Tacs 0x0 /* 0 clk */
97#define B5_Tcos 0x0 /* 0 clk */
98#define B5_Tacc 0x7 /* 14 clk */
99#define B5_Tcoh 0x0 /* 0 clk */
100#define B5_Tah 0x0 /* 0 clk */
101#define B5_Tacp 0x0
102#define B5_PMC 0x0 /* normal */
103
wdenkb0639ca2003-09-17 22:48:07 +0000104#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
105/* Bank6 */
106#define B6_MT 0x3 /* SDRAM */
dzubb65a312003-09-30 15:22:12 +0000107#define B6_Trcd 0x0 /* 2clk */
wdenkb0639ca2003-09-17 22:48:07 +0000108#define B6_SCAN 0x1 /* 9 bit */
109
110/* Bank7 */
111#define B7_MT 0x3 /* SDRAM */
dzubb65a312003-09-30 15:22:12 +0000112#define B7_Trcd 0x0 /* 2clk */
wdenkb0639ca2003-09-17 22:48:07 +0000113#define B7_SCAN 0x1 /* 9 bit */
114#else /* CONFIG_RAM_16MB = 16 MB RAM */
wdenkfe8c2802002-11-03 00:38:21 +0000115/* Bank6 */
116#define B6_MT 0x3 /* SDRAM */
117#define B6_Trcd 0x1 /* 2clk */
118#define B6_SCAN 0x0 /* 8 bit */
119
120/* Bank7 */
121#define B7_MT 0x3 /* SDRAM */
122#define B7_Trcd 0x1 /* 2clk */
123#define B7_SCAN 0x0 /* 8 bit */
wdenkb0639ca2003-09-17 22:48:07 +0000124#endif /* CONFIG_RAM_16MB */
wdenkfe8c2802002-11-03 00:38:21 +0000125
126/* refresh parameter */
127#define REFEN 0x1 /* enable refresh */
128#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
129#define Trp 0x0 /* 2 clk */
130#define Trc 0x3 /* 7 clk */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131#define Tchr 0x2 /* 3 clk */
wdenkfe8c2802002-11-03 00:38:21 +0000132
133#ifdef CONFIG_TRAB_50MHZ
134#define REFCNT 1269 /* period=15.6 us, HCLK=50Mhz, (2048+1-15.6*50) */
135#else
136#define REFCNT 1011 /* period=15.6 us, HCLK=66.5Mhz, (2048+1-15.6*66.5) */
137#endif
138
139
140_TEXT_BASE:
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200141 .word CONFIG_SYS_TEXT_BASE
wdenkfe8c2802002-11-03 00:38:21 +0000142
wdenk400558b2005-04-02 23:52:25 +0000143.globl lowlevel_init
144lowlevel_init:
wdenkfe8c2802002-11-03 00:38:21 +0000145 /* memory control configuration */
146 /* make r0 relative the current location so that it */
147 /* reads SMRDATA out of FLASH rather than memory ! */
148 ldr r0, =SMRDATA
149 ldr r1, _TEXT_BASE
150 sub r0, r0, r1
151 ldr r1, =BWSCON /* Bus Width Status Controller */
152 add r2, r0, #52
1530:
154 ldr r3, [r0], #4
155 str r3, [r1], #4
156 cmp r2, r0
157 bne 0b
158
159 /* everything is fine now */
160 mov pc, lr
161
162 .ltorg
163/* the literal pools origin */
164
165SMRDATA:
166 .word 0x2211d644 /* d->Ethernet, 6->CPLD, 4->SRAM, 4->FLASH */
167 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) /* GCS0 */
168 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) /* GCS1 */
169 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) /* GCS2 */
170 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) /* GCS3 */
171 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) /* GCS4 */
172 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) /* GCS5 */
173 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) /* GCS6 */
174 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) /* GCS7 */
175 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
wdenkb0639ca2003-09-17 22:48:07 +0000176#ifndef CONFIG_RAM_16MB /* 32 MB RAM */
177 .word 0x10 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 32M/32M */
178#else /* CONFIG_RAM_16MB = 16 MB RAM */
wdenkfe8c2802002-11-03 00:38:21 +0000179 .word 0x17 /* BUSWIDTH=32, SCLK power saving mode, BANKSIZE 16M/16M */
wdenkb0639ca2003-09-17 22:48:07 +0000180#endif /* CONFIG_RAM_16MB */
dzubb65a312003-09-30 15:22:12 +0000181 .word 0x20 /* MRSR6, CL=2clk */
182 .word 0x20 /* MRSR7 */