blob: 19d9b0b899c83dd2470a9d03b10000e16149bc1e [file] [log] [blame]
Jaehoon Chung757bff42012-10-15 19:10:29 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 * Rajeshawari Shinde <rajeshwari.s@samsung.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chung757bff42012-10-15 19:10:29 +00007 */
8
9#include <common.h>
10#include <malloc.h>
11#include <mmc.h>
12#include <dwmmc.h>
Jaehoon Chung757bff42012-10-15 19:10:29 +000013#include <asm-generic/errno.h>
14
15#define PAGE_SIZE 4096
16
17static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
18{
19 unsigned long timeout = 1000;
20 u32 ctrl;
21
22 dwmci_writel(host, DWMCI_CTRL, value);
23
24 while (timeout--) {
25 ctrl = dwmci_readl(host, DWMCI_CTRL);
26 if (!(ctrl & DWMCI_RESET_ALL))
27 return 1;
28 }
29 return 0;
30}
31
32static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
33 u32 desc0, u32 desc1, u32 desc2)
34{
35 struct dwmci_idmac *desc = idmac;
36
37 desc->flags = desc0;
38 desc->cnt = desc1;
39 desc->addr = desc2;
40 desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
41}
42
43static void dwmci_prepare_data(struct dwmci_host *host,
Mischa Jonker2136d222013-07-26 14:08:14 +020044 struct mmc_data *data, struct dwmci_idmac *cur_idmac)
Jaehoon Chung757bff42012-10-15 19:10:29 +000045{
46 unsigned long ctrl;
47 unsigned int i = 0, flags, cnt, blk_cnt;
48 ulong data_start, data_end, start_addr;
Jaehoon Chung757bff42012-10-15 19:10:29 +000049
50
51 blk_cnt = data->blocks;
52
53 dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
54
55 data_start = (ulong)cur_idmac;
56 dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
57
58 if (data->flags == MMC_DATA_READ)
59 start_addr = (unsigned int)data->dest;
60 else
61 start_addr = (unsigned int)data->src;
62
63 do {
64 flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
65 flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
66 if (blk_cnt <= 8) {
67 flags |= DWMCI_IDMAC_LD;
68 cnt = data->blocksize * blk_cnt;
69 } else
70 cnt = data->blocksize * 8;
71
72 dwmci_set_idma_desc(cur_idmac, flags, cnt,
73 start_addr + (i * PAGE_SIZE));
74
Mischa Jonker21bd5762013-07-26 16:18:40 +020075 if (blk_cnt <= 8)
Jaehoon Chung757bff42012-10-15 19:10:29 +000076 break;
77 blk_cnt -= 8;
78 cur_idmac++;
79 i++;
80 } while(1);
81
82 data_end = (ulong)cur_idmac;
83 flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
84
85 ctrl = dwmci_readl(host, DWMCI_CTRL);
86 ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
87 dwmci_writel(host, DWMCI_CTRL, ctrl);
88
89 ctrl = dwmci_readl(host, DWMCI_BMOD);
90 ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
91 dwmci_writel(host, DWMCI_BMOD, ctrl);
92
93 dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
94 dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
95}
96
97static int dwmci_set_transfer_mode(struct dwmci_host *host,
98 struct mmc_data *data)
99{
100 unsigned long mode;
101
102 mode = DWMCI_CMD_DATA_EXP;
103 if (data->flags & MMC_DATA_WRITE)
104 mode |= DWMCI_CMD_RW;
105
106 return mode;
107}
108
109static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
110 struct mmc_data *data)
111{
112 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
Mischa Jonker2136d222013-07-26 14:08:14 +0200113 ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
Mischa Jonker21bd5762013-07-26 16:18:40 +0200114 data ? DIV_ROUND_UP(data->blocks, 8) : 0);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000115 int flags = 0, i;
116 unsigned int timeout = 100000;
117 u32 retry = 10000;
118 u32 mask, ctrl;
Amar9c50e352013-04-27 11:42:54 +0530119 ulong start = get_timer(0);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000120
121 while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
Amar9c50e352013-04-27 11:42:54 +0530122 if (get_timer(start) > timeout) {
Jaehoon Chung757bff42012-10-15 19:10:29 +0000123 printf("Timeout on data busy\n");
124 return TIMEOUT;
125 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000126 }
127
128 dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
129
130 if (data)
Mischa Jonker2136d222013-07-26 14:08:14 +0200131 dwmci_prepare_data(host, data, cur_idmac);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000132
Jaehoon Chung757bff42012-10-15 19:10:29 +0000133 dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
134
135 if (data)
136 flags = dwmci_set_transfer_mode(host, data);
137
138 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
139 return -1;
140
141 if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
142 flags |= DWMCI_CMD_ABORT_STOP;
143 else
144 flags |= DWMCI_CMD_PRV_DAT_WAIT;
145
146 if (cmd->resp_type & MMC_RSP_PRESENT) {
147 flags |= DWMCI_CMD_RESP_EXP;
148 if (cmd->resp_type & MMC_RSP_136)
149 flags |= DWMCI_CMD_RESP_LENGTH;
150 }
151
152 if (cmd->resp_type & MMC_RSP_CRC)
153 flags |= DWMCI_CMD_CHECK_CRC;
154
155 flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
156
157 debug("Sending CMD%d\n",cmd->cmdidx);
158
159 dwmci_writel(host, DWMCI_CMD, flags);
160
161 for (i = 0; i < retry; i++) {
162 mask = dwmci_readl(host, DWMCI_RINTSTS);
163 if (mask & DWMCI_INTMSK_CDONE) {
164 if (!data)
165 dwmci_writel(host, DWMCI_RINTSTS, mask);
166 break;
167 }
168 }
169
170 if (i == retry)
171 return TIMEOUT;
172
173 if (mask & DWMCI_INTMSK_RTO) {
174 debug("Response Timeout..\n");
175 return TIMEOUT;
176 } else if (mask & DWMCI_INTMSK_RE) {
177 debug("Response Error..\n");
178 return -1;
179 }
180
181
182 if (cmd->resp_type & MMC_RSP_PRESENT) {
183 if (cmd->resp_type & MMC_RSP_136) {
184 cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
185 cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
186 cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
187 cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
188 } else {
189 cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
190 }
191 }
192
193 if (data) {
194 do {
195 mask = dwmci_readl(host, DWMCI_RINTSTS);
196 if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
197 debug("DATA ERROR!\n");
198 return -1;
199 }
200 } while (!(mask & DWMCI_INTMSK_DTO));
201
202 dwmci_writel(host, DWMCI_RINTSTS, mask);
203
204 ctrl = dwmci_readl(host, DWMCI_CTRL);
205 ctrl &= ~(DWMCI_DMA_EN);
206 dwmci_writel(host, DWMCI_CTRL, ctrl);
207 }
208
209 udelay(100);
210
211 return 0;
212}
213
214static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
215{
216 u32 div, status;
217 int timeout = 10000;
218 unsigned long sclk;
219
Amar9c50e352013-04-27 11:42:54 +0530220 if ((freq == host->clock) || (freq == 0))
Jaehoon Chung757bff42012-10-15 19:10:29 +0000221 return 0;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000222 /*
Jaehoon Chungb44fe832013-10-06 18:59:31 +0900223 * If host->get_mmc_clk didn't define,
Jaehoon Chung757bff42012-10-15 19:10:29 +0000224 * then assume that host->bus_hz is source clock value.
225 * host->bus_hz should be set from user.
226 */
Jaehoon Chungb44fe832013-10-06 18:59:31 +0900227 if (host->get_mmc_clk)
228 sclk = host->get_mmc_clk(host->dev_index);
Jaehoon Chung757bff42012-10-15 19:10:29 +0000229 else if (host->bus_hz)
230 sclk = host->bus_hz;
231 else {
232 printf("Didn't get source clock value..\n");
233 return -EINVAL;
234 }
235
236 div = DIV_ROUND_UP(sclk, 2 * freq);
237
238 dwmci_writel(host, DWMCI_CLKENA, 0);
239 dwmci_writel(host, DWMCI_CLKSRC, 0);
240
241 dwmci_writel(host, DWMCI_CLKDIV, div);
242 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
243 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
244
245 do {
246 status = dwmci_readl(host, DWMCI_CMD);
247 if (timeout-- < 0) {
248 printf("TIMEOUT error!!\n");
249 return -ETIMEDOUT;
250 }
251 } while (status & DWMCI_CMD_START);
252
253 dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
254 DWMCI_CLKEN_LOW_PWR);
255
256 dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
257 DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
258
259 timeout = 10000;
260 do {
261 status = dwmci_readl(host, DWMCI_CMD);
262 if (timeout-- < 0) {
263 printf("TIMEOUT error!!\n");
264 return -ETIMEDOUT;
265 }
266 } while (status & DWMCI_CMD_START);
267
268 host->clock = freq;
269
270 return 0;
271}
272
273static void dwmci_set_ios(struct mmc *mmc)
274{
275 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
276 u32 ctype;
277
278 debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
279
280 dwmci_setup_bus(host, mmc->clock);
281 switch (mmc->bus_width) {
282 case 8:
283 ctype = DWMCI_CTYPE_8BIT;
284 break;
285 case 4:
286 ctype = DWMCI_CTYPE_4BIT;
287 break;
288 default:
289 ctype = DWMCI_CTYPE_1BIT;
290 break;
291 }
292
293 dwmci_writel(host, DWMCI_CTYPE, ctype);
294
295 if (host->clksel)
296 host->clksel(host);
297}
298
299static int dwmci_init(struct mmc *mmc)
300{
301 struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
Jaehoon Chung757bff42012-10-15 19:10:29 +0000302
Jaehoon Chung18ab6752013-11-29 20:08:57 +0900303 if (host->board_init)
304 host->board_init(host);
Rajeshwari Shinde6f0b7ca2013-10-29 12:53:13 +0530305
Jaehoon Chung757bff42012-10-15 19:10:29 +0000306 dwmci_writel(host, DWMCI_PWREN, 1);
307
308 if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
309 debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
310 return -1;
311 }
312
Amar9c50e352013-04-27 11:42:54 +0530313 /* Enumerate at 400KHz */
314 dwmci_setup_bus(host, mmc->f_min);
315
Jaehoon Chung757bff42012-10-15 19:10:29 +0000316 dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
317 dwmci_writel(host, DWMCI_INTMASK, 0);
318
319 dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
320
321 dwmci_writel(host, DWMCI_IDINTEN, 0);
322 dwmci_writel(host, DWMCI_BMOD, 1);
323
Alexey Brodkin9108b312013-11-27 17:00:52 +0400324 if (host->fifoth_val) {
325 dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
Amar9c50e352013-04-27 11:42:54 +0530326 }
Jaehoon Chung757bff42012-10-15 19:10:29 +0000327
328 dwmci_writel(host, DWMCI_CLKENA, 0);
329 dwmci_writel(host, DWMCI_CLKSRC, 0);
330
331 return 0;
332}
333
334int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
335{
336 struct mmc *mmc;
337 int err = 0;
338
339 mmc = malloc(sizeof(struct mmc));
340 if (!mmc) {
341 printf("mmc malloc fail!\n");
342 return -1;
343 }
344
345 mmc->priv = host;
346 host->mmc = mmc;
347
348 sprintf(mmc->name, "%s", host->name);
349 mmc->send_cmd = dwmci_send_cmd;
350 mmc->set_ios = dwmci_set_ios;
351 mmc->init = dwmci_init;
352 mmc->f_min = min_clk;
353 mmc->f_max = max_clk;
354
355 mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
356
357 mmc->host_caps = host->caps;
358
359 if (host->buswidth == 8) {
360 mmc->host_caps |= MMC_MODE_8BIT;
361 mmc->host_caps &= ~MMC_MODE_4BIT;
362 } else {
363 mmc->host_caps |= MMC_MODE_4BIT;
364 mmc->host_caps &= ~MMC_MODE_8BIT;
365 }
366 mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
367
368 err = mmc_register(mmc);
369
370 return err;
371}