blob: 9e4c6c9078817dca12650b1548ea3b422469bf31 [file] [log] [blame]
Mingkai Hu234a89d2009-09-22 14:53:21 +08001/*
2 * Copyright 2009 Freescale Semiconductor, Inc.
3 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Mingkai Hu234a89d2009-09-22 14:53:21 +08005 */
6
7#include <common.h>
Scott Wood59629c22012-08-17 19:46:29 -05008#include <asm/processor.h>
9#include <asm/global_data.h>
York Sun0b665132013-10-22 12:39:02 -070010#include <fsl_ifc.h>
Mingkai Hu234a89d2009-09-22 14:53:21 +080011#include <asm/io.h>
12
Scott Wood59629c22012-08-17 19:46:29 -050013DECLARE_GLOBAL_DATA_PTR;
14
Mingkai Hu234a89d2009-09-22 14:53:21 +080015void cpu_init_f(void)
16{
Scott Woodc97cd1b2012-09-20 19:02:18 -050017#ifdef CONFIG_SYS_INIT_L2_ADDR
Mingkai Hu234a89d2009-09-22 14:53:21 +080018 ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
Mingkai Hu234a89d2009-09-22 14:53:21 +080019
20 out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
21
22 /* set MBECCDIS=1, SBECCDIS=1 */
23 out_be32(&l2cache->l2errdis,
24 (MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC));
25
26 /* set L2E=1 & L2SRAM=001 */
27 out_be32(&l2cache->l2ctl,
28 (MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
Mingkai Hu234a89d2009-09-22 14:53:21 +080029#endif
30}
Scott Wood59629c22012-08-17 19:46:29 -050031
32#ifndef CONFIG_SYS_FSL_TBCLK_DIV
33#define CONFIG_SYS_FSL_TBCLK_DIV 8
34#endif
35
36void udelay(unsigned long usec)
37{
38 u32 ticks_per_usec = gd->bus_clk / (CONFIG_SYS_FSL_TBCLK_DIV * 1000000);
39 u32 ticks = ticks_per_usec * usec;
40 u32 s = mfspr(SPRN_TBRL);
41
42 while ((mfspr(SPRN_TBRL) - s) < ticks);
43}