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Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +05301/*
2 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * Based on da830evm.c. Original Copyrights follow:
5 *
6 * Copyright (C) 2009 Nick Thompson, GE Fanuc, Ltd. <nick.thompson@gefanuc.com>
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <common.h>
25#include <i2c.h>
Ben Gardiner3d248d32010-10-14 17:26:29 -040026#include <net.h>
27#include <netdev.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053028#include <asm/arch/hardware.h>
Ben Gardinera3f88292010-10-14 17:26:22 -040029#include <asm/arch/emif_defs.h>
Ben Gardiner3d248d32010-10-14 17:26:29 -040030#include <asm/arch/emac_defs.h>
Christian Riesch52b0f872011-11-28 23:46:18 +000031#include <asm/arch/pinmux_defs.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053032#include <asm/io.h>
Sughosh Ganud7f9b502010-11-28 20:21:27 -050033#include <asm/arch/davinci_misc.h>
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -040034#include <hwconfig.h>
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +053035
36DECLARE_GLOBAL_DATA_PTR;
37
Ben Gardiner3d248d32010-10-14 17:26:29 -040038#ifdef CONFIG_DRIVER_TI_EMAC
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -050039#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
40#define HAS_RMII 1
41#else
42#define HAS_RMII 0
43#endif
44#endif /* CONFIG_DRIVER_TI_EMAC */
45
Nagabhushana Netaguntecf2c24e2011-09-03 22:19:28 -040046void dsp_lpsc_on(unsigned domain, unsigned int id)
47{
48 dv_reg_p mdstat, mdctl, ptstat, ptcmd;
49 struct davinci_psc_regs *psc_regs;
50
51 psc_regs = davinci_psc0_regs;
52 mdstat = &psc_regs->psc0.mdstat[id];
53 mdctl = &psc_regs->psc0.mdctl[id];
54 ptstat = &psc_regs->ptstat;
55 ptcmd = &psc_regs->ptcmd;
56
57 while (*ptstat & (0x1 << domain))
58 ;
59
60 if ((*mdstat & 0x1f) == 0x03)
61 return; /* Already on and enabled */
62
63 *mdctl |= 0x03;
64
65 *ptcmd = 0x1 << domain;
66
67 while (*ptstat & (0x1 << domain))
68 ;
69 while ((*mdstat & 0x1f) != 0x03)
70 ; /* Probably an overkill... */
71}
72
73static void dspwake(void)
74{
75 unsigned *resetvect = (unsigned *)DAVINCI_L3CBARAM_BASE;
76 u32 val;
77
78 /* if the device is ARM only, return */
79 if ((readl(CHIP_REV_ID_REG) & 0x3f) == 0x10)
80 return;
81
82 if (hwconfig_subarg_cmp_f("dsp", "wake", "no", NULL))
83 return;
84
85 *resetvect++ = 0x1E000; /* DSP Idle */
86 /* clear out the next 10 words as NOP */
87 memset(resetvect, 0, sizeof(unsigned) *10);
88
89 /* setup the DSP reset vector */
90 writel(DAVINCI_L3CBARAM_BASE, HOST1CFG);
91
92 dsp_lpsc_on(1, DAVINCI_LPSC_GEM);
93 val = readl(PSC0_MDCTL + (15 * 4));
94 val |= 0x100;
95 writel(val, (PSC0_MDCTL + (15 * 4)));
96}
97
98int misc_init_r(void)
99{
100 dspwake();
101 return 0;
102}
103
Christian Riesch52b0f872011-11-28 23:46:18 +0000104static const struct pinmux_config gpio_pins[] = {
105#ifdef CONFIG_USE_NOR
106 /* GP0[11] is required for NOR to work on Rev 3 EVMs */
107 { pinmux(0), 8, 4 }, /* GP0[11] */
108#endif
109};
110
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530111static const struct pinmux_resource pinmuxes[] = {
Christian Riesch591d8012011-11-28 23:46:16 +0000112#ifdef CONFIG_DRIVER_TI_EMAC
Christian Riesch52b0f872011-11-28 23:46:18 +0000113 PINMUX_ITEM(emac_pins_mdio),
114#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
115 PINMUX_ITEM(emac_pins_rmii),
116#else
117 PINMUX_ITEM(emac_pins_mii),
118#endif
Christian Riesch591d8012011-11-28 23:46:16 +0000119#endif
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530120#ifdef CONFIG_SPI_FLASH
Christian Riesch52b0f872011-11-28 23:46:18 +0000121 PINMUX_ITEM(spi1_pins_base),
122 PINMUX_ITEM(spi1_pins_scs0),
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530123#endif
Christian Riesch52b0f872011-11-28 23:46:18 +0000124 PINMUX_ITEM(uart2_pins_txrx),
125 PINMUX_ITEM(uart2_pins_rtscts),
126 PINMUX_ITEM(i2c0_pins),
Ben Gardiner756d1fe2010-10-14 17:26:19 -0400127#ifdef CONFIG_NAND_DAVINCI
Christian Riesch52b0f872011-11-28 23:46:18 +0000128 PINMUX_ITEM(emifa_pins_cs3),
129 PINMUX_ITEM(emifa_pins_cs4),
130 PINMUX_ITEM(emifa_pins_nand),
Nagabhushana Netagunte1506b0a2011-09-03 22:18:32 -0400131#elif defined(CONFIG_USE_NOR)
Christian Riesch52b0f872011-11-28 23:46:18 +0000132 PINMUX_ITEM(emifa_pins_cs2),
133 PINMUX_ITEM(emifa_pins_nor),
Ben Gardiner756d1fe2010-10-14 17:26:19 -0400134#endif
Christian Riesch52b0f872011-11-28 23:46:18 +0000135 PINMUX_ITEM(gpio_pins),
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530136};
137
138static const struct lpsc_resource lpsc[] = {
139 { DAVINCI_LPSC_AEMIF }, /* NAND, NOR */
140 { DAVINCI_LPSC_SPI1 }, /* Serial Flash */
141 { DAVINCI_LPSC_EMAC }, /* image download */
142 { DAVINCI_LPSC_UART2 }, /* console */
143 { DAVINCI_LPSC_GPIO },
144};
145
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500146#ifndef CONFIG_DA850_EVM_MAX_CPU_CLK
147#define CONFIG_DA850_EVM_MAX_CPU_CLK 300000000
148#endif
149
Manjunath Hadli754f8cb2011-10-10 21:06:38 +0000150#define REV_AM18X_EVM 0x100
151
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500152/*
153 * get_board_rev() - setup to pass kernel board revision information
154 * Returns:
155 * bit[0-3] Maximum cpu clock rate supported by onboard SoC
156 * 0000b - 300 MHz
157 * 0001b - 372 MHz
158 * 0010b - 408 MHz
159 * 0011b - 456 MHz
160 */
161u32 get_board_rev(void)
162{
163 char *s;
164 u32 maxcpuclk = CONFIG_DA850_EVM_MAX_CPU_CLK;
165 u32 rev = 0;
166
167 s = getenv("maxcpuclk");
168 if (s)
169 maxcpuclk = simple_strtoul(s, NULL, 10);
170
171 if (maxcpuclk >= 456000000)
172 rev = 3;
173 else if (maxcpuclk >= 408000000)
174 rev = 2;
175 else if (maxcpuclk >= 372000000)
176 rev = 1;
Manjunath Hadli754f8cb2011-10-10 21:06:38 +0000177#ifdef CONFIG_DA850_AM18X_EVM
178 rev |= REV_AM18X_EVM;
179#endif
Sekhar Nori4f6fc152010-11-19 11:39:48 -0500180 return rev;
181}
182
Christian Rieschae5c77d2011-10-13 00:52:29 +0000183int board_early_init_f(void)
184{
185 /*
186 * Power on required peripherals
187 * ARM does not have access by default to PSC0 and PSC1
188 * assuming here that the DSP bootloader has set the IOPU
189 * such that PSC access is available to ARM
190 */
191 if (da8xx_configure_lpsc_items(lpsc, ARRAY_SIZE(lpsc)))
192 return 1;
193
194 return 0;
195}
196
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530197int board_init(void)
198{
Wolfgang Denk6f0d7ae2011-09-05 05:26:27 +0000199#ifdef CONFIG_USE_NOR
Nagabhushana Netagunte0f3d6b02011-09-03 22:21:04 -0400200 u32 val;
Wolfgang Denk6f0d7ae2011-09-05 05:26:27 +0000201#endif
202
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530203#ifndef CONFIG_USE_IRQ
204 irq_init();
205#endif
206
Ben Gardinera3f88292010-10-14 17:26:22 -0400207#ifdef CONFIG_NAND_DAVINCI
208 /*
209 * NAND CS setup - cycle counts based on da850evm NAND timings in the
210 * Linux kernel @ 25MHz EMIFA
211 */
212 writel((DAVINCI_ABCR_WSETUP(0) |
Ben Gardiner24a514c2011-04-20 16:25:06 -0400213 DAVINCI_ABCR_WSTROBE(1) |
Ben Gardinera3f88292010-10-14 17:26:22 -0400214 DAVINCI_ABCR_WHOLD(0) |
215 DAVINCI_ABCR_RSETUP(0) |
216 DAVINCI_ABCR_RSTROBE(1) |
217 DAVINCI_ABCR_RHOLD(0) |
Ben Gardiner24a514c2011-04-20 16:25:06 -0400218 DAVINCI_ABCR_TA(1) |
Ben Gardinera3f88292010-10-14 17:26:22 -0400219 DAVINCI_ABCR_ASIZE_8BIT),
220 &davinci_emif_regs->ab2cr); /* CS3 */
221#endif
222
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530223 /* arch number of the board */
224 gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DA850_EVM;
225
226 /* address of boot parameters */
227 gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
228
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530229 /* setup the SUSPSRC for ARM to control emulation suspend */
230 writel(readl(&davinci_syscfg_regs->suspsrc) &
231 ~(DAVINCI_SYSCFG_SUSPSRC_EMAC | DAVINCI_SYSCFG_SUSPSRC_I2C |
232 DAVINCI_SYSCFG_SUSPSRC_SPI1 | DAVINCI_SYSCFG_SUSPSRC_TIMER0 |
233 DAVINCI_SYSCFG_SUSPSRC_UART2),
234 &davinci_syscfg_regs->suspsrc);
235
236 /* configure pinmux settings */
237 if (davinci_configure_pin_mux_items(pinmuxes, ARRAY_SIZE(pinmuxes)))
238 return 1;
239
Nagabhushana Netagunte0f3d6b02011-09-03 22:21:04 -0400240#ifdef CONFIG_USE_NOR
241 /* Set the GPIO direction as output */
242 clrbits_be32((u32 *)GPIO_BANK0_REG_DIR_ADDR, (0x01 << 11));
243
244 /* Set the output as low */
245 val = readl(GPIO_BANK0_REG_SET_ADDR);
246 val |= (0x01 << 11);
247 writel(val, GPIO_BANK0_REG_CLR_ADDR);
248#endif
249
Ben Gardiner3d248d32010-10-14 17:26:29 -0400250#ifdef CONFIG_DRIVER_TI_EMAC
Stefano Babic6d1c6492010-11-30 11:32:10 -0500251 davinci_emac_mii_mode_sel(HAS_RMII);
Ben Gardiner3d248d32010-10-14 17:26:29 -0400252#endif /* CONFIG_DRIVER_TI_EMAC */
253
Sudhakar Rajashekhara89b765c2010-06-10 15:18:15 +0530254 /* enable the console UART */
255 writel((DAVINCI_UART_PWREMU_MGMT_FREE | DAVINCI_UART_PWREMU_MGMT_URRST |
256 DAVINCI_UART_PWREMU_MGMT_UTRST),
257 &davinci_uart2_ctrl_regs->pwremu_mgmt);
258
259 return 0;
260}
Ben Gardiner3d248d32010-10-14 17:26:29 -0400261
262#ifdef CONFIG_DRIVER_TI_EMAC
263
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500264#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
265/**
266 * rmii_hw_init
267 *
268 * DA850/OMAP-L138 EVM can interface to a daughter card for
269 * additional features. This card has an I2C GPIO Expander TCA6416
270 * to select the required functions like camera, RMII Ethernet,
271 * character LCD, video.
272 *
273 * Initialization of the expander involves configuring the
274 * polarity and direction of the ports. P07-P05 are used here.
275 * These ports are connected to a Mux chip which enables only one
276 * functionality at a time.
277 *
278 * For RMII phy to respond, the MII MDIO clock has to be disabled
279 * since both the PHY devices have address as zero. The MII MDIO
280 * clock is controlled via GPIO2[6].
281 *
282 * This code is valid for Beta version of the hardware
283 */
284int rmii_hw_init(void)
285{
286 const struct pinmux_config gpio_pins[] = {
287 { pinmux(6), 8, 1 }
288 };
289 u_int8_t buf[2];
290 unsigned int temp;
291 int ret;
292
293 /* PinMux for GPIO */
294 if (davinci_configure_pin_mux(gpio_pins, ARRAY_SIZE(gpio_pins)) != 0)
295 return 1;
296
297 /* I2C Exapnder configuration */
298 /* Set polarity to non-inverted */
299 buf[0] = 0x0;
300 buf[1] = 0x0;
301 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 4, 1, buf, 2);
302 if (ret) {
303 printf("\nExpander @ 0x%02x write FAILED!!!\n",
304 CONFIG_SYS_I2C_EXPANDER_ADDR);
305 return ret;
306 }
307
308 /* Configure P07-P05 as outputs */
309 buf[0] = 0x1f;
310 buf[1] = 0xff;
311 ret = i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 6, 1, buf, 2);
312 if (ret) {
313 printf("\nExpander @ 0x%02x write FAILED!!!\n",
314 CONFIG_SYS_I2C_EXPANDER_ADDR);
315 }
316
317 /* For Ethernet RMII selection
318 * P07(SelA)=0
319 * P06(SelB)=1
320 * P05(SelC)=1
321 */
322 if (i2c_read(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
323 printf("\nExpander @ 0x%02x read FAILED!!!\n",
324 CONFIG_SYS_I2C_EXPANDER_ADDR);
325 }
326
327 buf[0] &= 0x1f;
328 buf[0] |= (0 << 7) | (1 << 6) | (1 << 5);
329 if (i2c_write(CONFIG_SYS_I2C_EXPANDER_ADDR, 2, 1, buf, 1)) {
330 printf("\nExpander @ 0x%02x write FAILED!!!\n",
331 CONFIG_SYS_I2C_EXPANDER_ADDR);
332 }
333
334 /* Set the output as high */
335 temp = REG(GPIO_BANK2_REG_SET_ADDR);
336 temp |= (0x01 << 6);
337 REG(GPIO_BANK2_REG_SET_ADDR) = temp;
338
339 /* Set the GPIO direction as output */
340 temp = REG(GPIO_BANK2_REG_DIR_ADDR);
341 temp &= ~(0x01 << 6);
342 REG(GPIO_BANK2_REG_DIR_ADDR) = temp;
343
344 return 0;
345}
346#endif /* CONFIG_DRIVER_TI_EMAC_USE_RMII */
347
Ben Gardiner3d248d32010-10-14 17:26:29 -0400348/*
349 * Initializes on-board ethernet controllers.
350 */
351int board_eth_init(bd_t *bis)
352{
Sudhakar Rajashekharad2607402010-11-18 09:59:37 -0500353#ifdef CONFIG_DRIVER_TI_EMAC_USE_RMII
354 /* Select RMII fucntion through the expander */
355 if (rmii_hw_init())
356 printf("RMII hardware init failed!!!\n");
357#endif
Ben Gardiner3d248d32010-10-14 17:26:29 -0400358 if (!davinci_emac_initialize()) {
359 printf("Error: Ethernet init failed!\n");
360 return -1;
361 }
362
363 return 0;
364}
365#endif /* CONFIG_DRIVER_TI_EMAC */