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wdenkf8cac652002-08-26 22:36:39 +00001/*
Wolfgang Denk8cba0902006-05-12 16:15:46 +02002 * (C) Copyright 2000-2006
wdenkf8cac652002-08-26 22:36:39 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
wdenkd4ca31c2004-01-02 14:00:00 +000024#if 0
25#define DEBUG
26#endif
27
wdenkf8cac652002-08-26 22:36:39 +000028#include <common.h>
29#include <mpc8xx.h>
wdenk1c437712004-01-16 00:30:56 +000030#ifdef CONFIG_PS2MULT
31#include <ps2mult.h>
32#endif
wdenkf8cac652002-08-26 22:36:39 +000033
Wolfgang Denkd87080b2006-03-31 18:32:53 +020034DECLARE_GLOBAL_DATA_PTR;
wdenkf8cac652002-08-26 22:36:39 +000035
36static long int dram_size (long int, long int *, long int);
37
wdenkf8cac652002-08-26 22:36:39 +000038#define _NOT_USED_ 0xFFFFFFFF
39
40const uint sdram_table[] =
41{
42 /*
43 * Single Read. (Offset 0 in UPMA RAM)
44 */
45 0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
46 0x1FF5FC47, /* last */
47 /*
48 * SDRAM Initialization (offset 5 in UPMA RAM)
49 *
50 * This is no UPM entry point. The following definition uses
51 * the remaining space to establish an initialization
52 * sequence, which is executed by a RUN command.
53 *
54 */
55 0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
56 /*
57 * Burst Read. (Offset 8 in UPMA RAM)
58 */
59 0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
60 0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
61 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
62 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
63 /*
64 * Single Write. (Offset 18 in UPMA RAM)
65 */
66 0x1F0DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
67 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
68 /*
69 * Burst Write. (Offset 20 in UPMA RAM)
70 */
71 0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
72 0xF0AFFC00, 0xE1BAFC04, 0x1FF5FC47, /* last */
73 _NOT_USED_,
74 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
75 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
76 /*
77 * Refresh (Offset 30 in UPMA RAM)
78 */
79 0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
80 0xFFFFFC84, 0xFFFFFC07, /* last */
81 _NOT_USED_, _NOT_USED_,
82 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
83 /*
84 * Exception. (Offset 3c in UPMA RAM)
85 */
86 0x7FFFFC07, /* last */
87 _NOT_USED_, _NOT_USED_, _NOT_USED_,
88};
89
90/* ------------------------------------------------------------------------- */
91
92
93/*
94 * Check Board Identity:
95 *
96 * Test TQ ID string (TQM8xx...)
97 * If present, check for "L" type (no second DRAM bank),
98 * otherwise "L" type is assumed as default.
99 *
wdenkd4ca31c2004-01-02 14:00:00 +0000100 * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
wdenkf8cac652002-08-26 22:36:39 +0000101 */
102
103int checkboard (void)
104{
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200105 char *s = getenv ("serial#");
wdenkf8cac652002-08-26 22:36:39 +0000106
107 puts ("Board: ");
108
109 if (!s || strncmp (s, "TQM8", 4)) {
110 puts ("### No HW ID - assuming TQM8xxL\n");
111 return (0);
112 }
113
114 if ((*(s + 6) == 'L')) { /* a TQM8xxL type */
115 gd->board_type = 'L';
116 }
117
wdenkd4ca31c2004-01-02 14:00:00 +0000118 if ((*(s + 6) == 'M')) { /* a TQM8xxM type */
119 gd->board_type = 'M';
120 }
121
wdenkf8cac652002-08-26 22:36:39 +0000122 for (; *s; ++s) {
123 if (*s == ' ')
124 break;
125 putc (*s);
126 }
Wolfgang Denk8cba0902006-05-12 16:15:46 +0200127#ifdef CONFIG_VIRTLAB2
128 puts (" (Virtlab2)");
129#endif
wdenkf8cac652002-08-26 22:36:39 +0000130 putc ('\n');
131
132 return (0);
133}
134
135/* ------------------------------------------------------------------------- */
136
137long int initdram (int board_type)
138{
139 volatile immap_t *immap = (immap_t *) CFG_IMMR;
140 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkc178d3d2004-01-24 20:25:54 +0000141 long int size8, size9, size10;
wdenkf8cac652002-08-26 22:36:39 +0000142 long int size_b0 = 0;
143 long int size_b1 = 0;
144
145 upmconfig (UPMA, (uint *) sdram_table,
146 sizeof (sdram_table) / sizeof (uint));
147
148 /*
149 * Preliminary prescaler for refresh (depends on number of
150 * banks): This value is selected for four cycles every 62.4 us
151 * with two SDRAM banks or four cycles every 31.2 us with one
152 * bank. It will be adjusted after memory sizing.
153 */
154 memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
155
156 /*
157 * The following value is used as an address (i.e. opcode) for
158 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
159 * the port size is 32bit the SDRAM does NOT "see" the lower two
160 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
161 * MICRON SDRAMs:
162 * -> 0 00 010 0 010
163 * | | | | +- Burst Length = 4
164 * | | | +----- Burst Type = Sequential
165 * | | +------- CAS Latency = 2
166 * | +----------- Operating Mode = Standard
167 * +-------------- Write Burst Mode = Programmed Burst Length
168 */
169 memctl->memc_mar = 0x00000088;
170
171 /*
172 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
173 * preliminary addresses - these have to be modified after the
174 * SDRAM size has been determined.
175 */
176 memctl->memc_or2 = CFG_OR2_PRELIM;
177 memctl->memc_br2 = CFG_BR2_PRELIM;
178
179#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000180 if ((board_type != 'L') &&
181 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
wdenkf8cac652002-08-26 22:36:39 +0000182 memctl->memc_or3 = CFG_OR3_PRELIM;
183 memctl->memc_br3 = CFG_BR3_PRELIM;
184 }
185#endif /* CONFIG_CAN_DRIVER */
186
187 memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
188
189 udelay (200);
190
191 /* perform SDRAM initializsation sequence */
192
193 memctl->memc_mcr = 0x80004105; /* SDRAM bank 0 */
194 udelay (1);
195 memctl->memc_mcr = 0x80004230; /* SDRAM bank 0 - execute twice */
196 udelay (1);
197
198#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000199 if ((board_type != 'L') &&
200 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
wdenkf8cac652002-08-26 22:36:39 +0000201 memctl->memc_mcr = 0x80006105; /* SDRAM bank 1 */
202 udelay (1);
203 memctl->memc_mcr = 0x80006230; /* SDRAM bank 1 - execute twice */
204 udelay (1);
205 }
206#endif /* CONFIG_CAN_DRIVER */
207
208 memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
209
210 udelay (1000);
211
212 /*
213 * Check Bank 0 Memory Size for re-configuration
214 *
215 * try 8 column mode
216 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200217 size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM,
wdenkf8cac652002-08-26 22:36:39 +0000218 SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000219 debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000220
221 udelay (1000);
222
223 /*
224 * try 9 column mode
225 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200226 size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM,
wdenkf8cac652002-08-26 22:36:39 +0000227 SDRAM_MAX_SIZE);
wdenkd4ca31c2004-01-02 14:00:00 +0000228 debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000229
wdenkc178d3d2004-01-24 20:25:54 +0000230 udelay(1000);
231
232#if defined(CFG_MAMR_10COL)
233 /*
234 * try 10 column mode
235 */
236 size10 = dram_size (CFG_MAMR_10COL, (ulong *) SDRAM_BASE2_PRELIM,
237 SDRAM_MAX_SIZE);
238 debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
239#else
240 size10 = 0;
241#endif /* CFG_MAMR_10COL */
242
243 if ((size8 < size10) && (size9 < size10)) {
244 size_b0 = size10;
245 } else if ((size8 < size9) && (size10 < size9)) {
wdenkf8cac652002-08-26 22:36:39 +0000246 size_b0 = size9;
wdenkc178d3d2004-01-24 20:25:54 +0000247 memctl->memc_mamr = CFG_MAMR_9COL;
248 udelay (500);
249 } else {
wdenkf8cac652002-08-26 22:36:39 +0000250 size_b0 = size8;
251 memctl->memc_mamr = CFG_MAMR_8COL;
252 udelay (500);
wdenkf8cac652002-08-26 22:36:39 +0000253 }
wdenkd4ca31c2004-01-02 14:00:00 +0000254 debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000255
256#ifndef CONFIG_CAN_DRIVER
wdenkd4ca31c2004-01-02 14:00:00 +0000257 if ((board_type != 'L') &&
258 (board_type != 'M') ) { /* "L" and "M" type boards have only one bank SDRAM */
wdenkf8cac652002-08-26 22:36:39 +0000259 /*
260 * Check Bank 1 Memory Size
261 * use current column settings
262 * [9 column SDRAM may also be used in 8 column mode,
263 * but then only half the real size will be used.]
264 */
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200265 size_b1 = dram_size (memctl->memc_mamr, (long int *)SDRAM_BASE3_PRELIM,
wdenkd4ca31c2004-01-02 14:00:00 +0000266 SDRAM_MAX_SIZE);
267 debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
wdenkf8cac652002-08-26 22:36:39 +0000268 } else {
269 size_b1 = 0;
270 }
wdenkd4ca31c2004-01-02 14:00:00 +0000271#endif /* CONFIG_CAN_DRIVER */
wdenkf8cac652002-08-26 22:36:39 +0000272
273 udelay (1000);
274
275 /*
276 * Adjust refresh rate depending on SDRAM type, both banks
277 * For types > 128 MBit leave it at the current (fast) rate
278 */
279 if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
280 /* reduce to 15.6 us (62.4 us / quad) */
281 memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
282 udelay (1000);
283 }
284
285 /*
286 * Final mapping: map bigger bank first
287 */
288 if (size_b1 > size_b0) { /* SDRAM Bank 1 is bigger - map first */
289
290 memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
wdenkc178d3d2004-01-24 20:25:54 +0000291 memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
wdenkf8cac652002-08-26 22:36:39 +0000292
293 if (size_b0 > 0) {
294 /*
295 * Position Bank 0 immediately above Bank 1
296 */
wdenkc178d3d2004-01-24 20:25:54 +0000297 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
298 memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
299 + size_b1;
wdenkf8cac652002-08-26 22:36:39 +0000300 } else {
301 unsigned long reg;
302
303 /*
304 * No bank 0
305 *
306 * invalidate bank
307 */
308 memctl->memc_br2 = 0;
309
310 /* adjust refresh rate depending on SDRAM type, one bank */
311 reg = memctl->memc_mptpr;
312 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
313 memctl->memc_mptpr = reg;
314 }
315
316 } else { /* SDRAM Bank 0 is bigger - map first */
317
318 memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
319 memctl->memc_br2 =
320 (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
321
322 if (size_b1 > 0) {
323 /*
324 * Position Bank 1 immediately above Bank 0
325 */
326 memctl->memc_or3 =
327 ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
328 memctl->memc_br3 =
329 ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
330 + size_b0;
331 } else {
332 unsigned long reg;
333
334#ifndef CONFIG_CAN_DRIVER
335 /*
336 * No bank 1
337 *
338 * invalidate bank
339 */
340 memctl->memc_br3 = 0;
341#endif /* CONFIG_CAN_DRIVER */
342
343 /* adjust refresh rate depending on SDRAM type, one bank */
344 reg = memctl->memc_mptpr;
345 reg >>= 1; /* reduce to CFG_MPTPR_1BK_8K / _4K */
346 memctl->memc_mptpr = reg;
347 }
348 }
349
350 udelay (10000);
351
352#ifdef CONFIG_CAN_DRIVER
353 /* Initialize OR3 / BR3 */
354 memctl->memc_or3 = CFG_OR3_CAN;
355 memctl->memc_br3 = CFG_BR3_CAN;
356
357 /* Initialize MBMR */
wdenkfd3103b2003-11-25 16:55:19 +0000358 memctl->memc_mbmr = MBMR_GPL_B4DIS; /* GPL_B4 ouput line Disable */
wdenkf8cac652002-08-26 22:36:39 +0000359
360 /* Initialize UPMB for CAN: single read */
361 memctl->memc_mdr = 0xFFFFC004;
362 memctl->memc_mcr = 0x0100 | UPMB;
363
364 memctl->memc_mdr = 0x0FFFD004;
365 memctl->memc_mcr = 0x0101 | UPMB;
366
367 memctl->memc_mdr = 0x0FFFC000;
368 memctl->memc_mcr = 0x0102 | UPMB;
369
370 memctl->memc_mdr = 0x3FFFC004;
371 memctl->memc_mcr = 0x0103 | UPMB;
372
373 memctl->memc_mdr = 0xFFFFDC05;
374 memctl->memc_mcr = 0x0104 | UPMB;
375
376 /* Initialize UPMB for CAN: single write */
377 memctl->memc_mdr = 0xFFFCC004;
378 memctl->memc_mcr = 0x0118 | UPMB;
379
380 memctl->memc_mdr = 0xCFFCD004;
381 memctl->memc_mcr = 0x0119 | UPMB;
382
383 memctl->memc_mdr = 0x0FFCC000;
384 memctl->memc_mcr = 0x011A | UPMB;
385
386 memctl->memc_mdr = 0x7FFCC004;
387 memctl->memc_mcr = 0x011B | UPMB;
388
389 memctl->memc_mdr = 0xFFFDCC05;
390 memctl->memc_mcr = 0x011C | UPMB;
391#endif /* CONFIG_CAN_DRIVER */
392
wdenkbdccc4f2003-08-05 17:43:17 +0000393#ifdef CONFIG_ISP1362_USB
394 /* Initialize OR5 / BR5 */
395 memctl->memc_or5 = CFG_OR5_ISP1362;
396 memctl->memc_br5 = CFG_BR5_ISP1362;
397#endif /* CONFIG_ISP1362_USB */
wdenk42d1f032003-10-15 23:53:47 +0000398
399
wdenkf8cac652002-08-26 22:36:39 +0000400 return (size_b0 + size_b1);
401}
402
403/* ------------------------------------------------------------------------- */
404
405/*
406 * Check memory range for valid RAM. A simple memory test determines
407 * the actually available RAM size between addresses `base' and
408 * `base + maxsize'. Some (not all) hardware errors are detected:
409 * - short between address lines
410 * - short between data lines
411 */
412
wdenkd4ca31c2004-01-02 14:00:00 +0000413static long int dram_size (long int mamr_value, long int *base, long int maxsize)
wdenkf8cac652002-08-26 22:36:39 +0000414{
415 volatile immap_t *immap = (immap_t *) CFG_IMMR;
416 volatile memctl8xx_t *memctl = &immap->im_memctl;
wdenkf8cac652002-08-26 22:36:39 +0000417
418 memctl->memc_mamr = mamr_value;
419
wdenkc83bf6a2004-01-06 22:38:14 +0000420 return (get_ram_size(base, maxsize));
wdenkf8cac652002-08-26 22:36:39 +0000421}
422
423/* ------------------------------------------------------------------------- */
wdenk1c437712004-01-16 00:30:56 +0000424
425#ifdef CONFIG_PS2MULT
426
wdenkc40b2952004-03-13 23:29:43 +0000427#ifdef CONFIG_HMI10
wdenk1c437712004-01-16 00:30:56 +0000428#define BASE_BAUD ( 1843200 / 16 )
429struct serial_state rs_table[] = {
430 { BASE_BAUD, 4, (void*)0xec140000 },
431 { BASE_BAUD, 2, (void*)0xec150000 },
432 { BASE_BAUD, 6, (void*)0xec160000 },
433 { BASE_BAUD, 10, (void*)0xec170000 },
434};
wdenkc837dcb2004-01-20 23:12:12 +0000435
436#ifdef CONFIG_BOARD_EARLY_INIT_R
437int board_early_init_r (void)
438{
439 ps2mult_early_init();
440 return (0);
441}
442#endif
wdenkc40b2952004-03-13 23:29:43 +0000443#endif /* CONFIG_HMI10 */
wdenk1c437712004-01-16 00:30:56 +0000444
445#endif /* CONFIG_PS2MULT */
446
wdenkcfca5e62004-08-01 13:09:47 +0000447/* ---------------------------------------------------------------------------- */
448/* HMI10 specific stuff */
449/* ---------------------------------------------------------------------------- */
wdenkc40b2952004-03-13 23:29:43 +0000450#ifdef CONFIG_HMI10
wdenk1c437712004-01-16 00:30:56 +0000451
452int misc_init_r (void)
453{
wdenkcfca5e62004-08-01 13:09:47 +0000454# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000455 volatile immap_t *immap = (immap_t *) CFG_IMMR;
456
457 /* Configure PA15 as output port */
458 immap->im_ioport.iop_padir |= 0x0001;
459 immap->im_ioport.iop_paodr |= 0x0001;
460 immap->im_ioport.iop_papar &= ~0x0001;
461 immap->im_ioport.iop_padat &= ~0x0001; /* turn it off */
wdenkcfca5e62004-08-01 13:09:47 +0000462# endif
wdenk1c437712004-01-16 00:30:56 +0000463 return (0);
464}
465
wdenkcfca5e62004-08-01 13:09:47 +0000466# ifdef CONFIG_IDE_LED
wdenk1c437712004-01-16 00:30:56 +0000467void ide_led (uchar led, uchar status)
468{
469 volatile immap_t *immap = (immap_t *) CFG_IMMR;
470
471 /* We have one led for both pcmcia slots */
472 if (status) { /* led on */
473 immap->im_ioport.iop_padat |= 0x0001;
474 } else {
475 immap->im_ioport.iop_padat &= ~0x0001;
476 }
477}
wdenkcfca5e62004-08-01 13:09:47 +0000478# endif
479#endif /* CONFIG_HMI10 */
wdenk1c437712004-01-16 00:30:56 +0000480
wdenkcfca5e62004-08-01 13:09:47 +0000481/* ---------------------------------------------------------------------------- */
482/* NSCU specific stuff */
483/* ---------------------------------------------------------------------------- */
484#ifdef CONFIG_NSCU
485
486int misc_init_r (void)
487{
488 volatile immap_t *immr = (immap_t *) CFG_IMMR;
489
490 /* wake up ethernet module */
491 immr->im_ioport.iop_pcpar &= ~0x0004; /* GPIO pin */
492 immr->im_ioport.iop_pcdir |= 0x0004; /* output */
493 immr->im_ioport.iop_pcso &= ~0x0004; /* for clarity */
494 immr->im_ioport.iop_pcdat |= 0x0004; /* enable */
495
496 return (0);
497}
498#endif /* CONFIG_NSCU */
499
wdenk1c437712004-01-16 00:30:56 +0000500/* ------------------------------------------------------------------------- */