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Vasily Khoruzhickf19eb152016-03-20 18:37:00 -07001/*
2 * Aeronix Zipit Z2 configuration file
3 *
4 * Copyright (C) 2009-2010 Marek Vasut <marek.vasut@gmail.com>
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12/*
13 * High Level Board Configuration Options
14 */
15#define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */
16#define CONFIG_SYS_TEXT_BASE 0x0
17
18#undef CONFIG_BOARD_LATE_INIT
19#undef CONFIG_SKIP_LOWLEVEL_INIT
20#define CONFIG_PREBOOT
21
22/*
23 * Environment settings
24 */
25#define CONFIG_ENV_OVERWRITE
26#define CONFIG_ENV_IS_IN_FLASH 1
27#define CONFIG_ENV_ADDR 0x40000
28#define CONFIG_ENV_SIZE 0x10000
29
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070030#define CONFIG_SYS_MALLOC_LEN (128*1024)
31#define CONFIG_ARCH_CPU_INIT
32
33#define CONFIG_BOOTCOMMAND \
34 "if mmc rescan && ext2load mmc 0 0xa0000000 boot/uboot.script ;"\
35 "then " \
36 "source 0xa0000000; " \
37 "else " \
38 "bootm 0x50000; " \
39 "fi; "
40#define CONFIG_BOOTARGS \
41 "console=tty0 console=ttyS2,115200 fbcon=rotate:3"
42#define CONFIG_TIMESTAMP
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070043#define CONFIG_CMDLINE_TAG
44#define CONFIG_SETUP_MEMORY_TAGS
45#define CONFIG_SYS_TEXT_BASE 0x0
46#define CONFIG_LZMA /* LZMA compression support */
47
48/*
49 * Serial Console Configuration
50 * STUART - the lower serial port on Colibri board
51 */
52#define CONFIG_PXA_SERIAL
53#define CONFIG_STUART 1
54#define CONFIG_CONS_INDEX 2
55#define CONFIG_BAUDRATE 115200
56
57/*
58 * Bootloader Components Configuration
59 */
60#define CONFIG_CMD_ENV
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070061
62/*
63 * MMC Card Configuration
64 */
65#ifdef CONFIG_CMD_MMC
66#define CONFIG_MMC
67#define CONFIG_GENERIC_MMC
68#define CONFIG_PXA_MMC_GENERIC
69#define CONFIG_SYS_MMC_BASE 0xF0000000
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070070#define CONFIG_DOS_PARTITION
71#endif
72
73/*
74 * SPI and LCD
75 */
76#ifdef CONFIG_CMD_SPI
77#define CONFIG_SOFT_SPI
78#define CONFIG_LCD
Vasily Khoruzhick59fa0892016-03-20 18:37:01 -070079#define CONFIG_LCD_ROTATION
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070080#define CONFIG_PXA_LCD
81#define CONFIG_LMS283GF05
82
83#define SPI_DELAY udelay(10)
84#define SPI_SDA(val) zipitz2_spi_sda(val)
85#define SPI_SCL(val) zipitz2_spi_scl(val)
86#define SPI_READ zipitz2_spi_read()
87#ifndef __ASSEMBLY__
88void zipitz2_spi_sda(int);
89void zipitz2_spi_scl(int);
90unsigned char zipitz2_spi_read(void);
91#endif
92#endif
93
Vasily Khoruzhickf19eb152016-03-20 18:37:00 -070094#define CONFIG_SYS_LONGHELP /* undef to save memory */
95#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
96#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
97#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
98#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
99#define CONFIG_SYS_DEVICE_NULLDEV 1
100
101/*
102 * Clock Configuration
103 */
104#define CONFIG_SYS_CPUSPEED 0x190 /* standard setting for 312MHz; L=16, N=1.5, A=0, SDCLK!=SystemBus */
105
106/*
107 * SRAM Map
108 */
109#define PHYS_SRAM 0x5c000000 /* SRAM Bank #1 */
110#define PHYS_SRAM_SIZE 0x00040000 /* 256k */
111
112/*
113 * DRAM Map
114 */
115#define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */
116#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
117#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
118
119#define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */
120#define CONFIG_SYS_DRAM_SIZE 0x02000000 /* 32 MB DRAM */
121
122#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
123#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
124
125#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
126
127#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
128#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SRAM + 2048)
129
130/*
131 * NOR FLASH
132 */
133#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
134#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
135#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors */
136#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
137
138#define CONFIG_SYS_FLASH_CFI
139#define CONFIG_FLASH_CFI_DRIVER 1
140#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
141
142#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
143#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE
144
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
146#define CONFIG_SYS_MAX_FLASH_SECT 256
147
148#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
149
150#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
151#define CONFIG_SYS_FLASH_WRITE_TOUT 240000
152#define CONFIG_SYS_FLASH_LOCK_TOUT 240000
153#define CONFIG_SYS_FLASH_UNLOCK_TOUT 240000
154#define CONFIG_SYS_FLASH_PROTECTION
155
156/*
157 * GPIO settings
158 */
159#define CONFIG_SYS_GAFR0_L_VAL 0x02000140
160#define CONFIG_SYS_GAFR0_U_VAL 0x59188000
161#define CONFIG_SYS_GAFR1_L_VAL 0x63900002
162#define CONFIG_SYS_GAFR1_U_VAL 0xaaa03950
163#define CONFIG_SYS_GAFR2_L_VAL 0x0aaaaaaa
164#define CONFIG_SYS_GAFR2_U_VAL 0x29000308
165#define CONFIG_SYS_GAFR3_L_VAL 0x54000000
166#define CONFIG_SYS_GAFR3_U_VAL 0x000000d5
167#define CONFIG_SYS_GPCR0_VAL 0x00000000
168#define CONFIG_SYS_GPCR1_VAL 0x00000020
169#define CONFIG_SYS_GPCR2_VAL 0x00000000
170#define CONFIG_SYS_GPCR3_VAL 0x00000000
171#define CONFIG_SYS_GPDR0_VAL 0xdafcee00
172#define CONFIG_SYS_GPDR1_VAL 0xffa3aaab
173#define CONFIG_SYS_GPDR2_VAL 0x8fe9ffff
174#define CONFIG_SYS_GPDR3_VAL 0x001b1f8a
175#define CONFIG_SYS_GPSR0_VAL 0x06080400
176#define CONFIG_SYS_GPSR1_VAL 0x007f0000
177#define CONFIG_SYS_GPSR2_VAL 0x032a0000
178#define CONFIG_SYS_GPSR3_VAL 0x00000180
179
180#define CONFIG_SYS_PSSR_VAL 0x30
181
182/*
183 * Clock settings
184 */
185#define CONFIG_SYS_CKEN 0x00511220
186#define CONFIG_SYS_CCCR 0x00000190
187
188/*
189 * Memory settings
190 */
191#define CONFIG_SYS_MSC0_VAL 0x2ffc38f8
192#define CONFIG_SYS_MSC1_VAL 0x0000ccd1
193#define CONFIG_SYS_MSC2_VAL 0x0000b884
194#define CONFIG_SYS_MDCNFG_VAL 0x08000ba9
195#define CONFIG_SYS_MDREFR_VAL 0x2011a01e
196#define CONFIG_SYS_MDMRS_VAL 0x00000000
197#define CONFIG_SYS_FLYCNFG_VAL 0x00010001
198#define CONFIG_SYS_SXCNFG_VAL 0x40044004
199
200/*
201 * PCMCIA and CF Interfaces
202 */
203#define CONFIG_SYS_MECR_VAL 0x00000001
204#define CONFIG_SYS_MCMEM0_VAL 0x00014307
205#define CONFIG_SYS_MCMEM1_VAL 0x00014307
206#define CONFIG_SYS_MCATT0_VAL 0x0001c787
207#define CONFIG_SYS_MCATT1_VAL 0x0001c787
208#define CONFIG_SYS_MCIO0_VAL 0x0001430f
209#define CONFIG_SYS_MCIO1_VAL 0x0001430f
210
211#include "pxa-common.h"
212
213#endif /* __CONFIG_H */