blob: 09cc9c5b9ce0a21bb26142b7fd247a81b5c97074 [file] [log] [blame]
Sascha Hauercaebc952008-03-26 20:41:09 +01001/*
2 *
3 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <common.h>
Ben Warren736fead2009-07-20 22:01:11 -070026#include <netdev.h>
Stefano Babic86271112011-03-14 15:43:56 +010027#include <asm/arch/clock.h>
28#include <asm/arch/imx-regs.h>
Sascha Hauercaebc952008-03-26 20:41:09 +010029
30DECLARE_GLOBAL_DATA_PTR;
31
Fabio Estevam4e377312011-06-05 14:56:02 +000032int dram_init(void)
Sascha Hauercaebc952008-03-26 20:41:09 +010033{
Fabio Estevam4e377312011-06-05 14:56:02 +000034 /* dram_init must store complete ramsize in gd->ram_size */
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000035 gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
Fabio Estevam4e377312011-06-05 14:56:02 +000036 PHYS_SDRAM_1_SIZE);
Sascha Hauercaebc952008-03-26 20:41:09 +010037 return 0;
38}
39
Fabio Estevam4e377312011-06-05 14:56:02 +000040void dram_init_banksize(void)
Magnus Lilja68a75d02010-10-16 19:47:06 +020041{
42 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
43 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
44}
45
Fabio Estevam4e377312011-06-05 14:56:02 +000046int board_early_init_f(void)
Sascha Hauercaebc952008-03-26 20:41:09 +010047{
48 __REG(CSCR_U(0)) = 0x0000cf03; /* CS0: Nor Flash */
49 __REG(CSCR_L(0)) = 0xa0330d01;
50 __REG(CSCR_A(0)) = 0x00220800;
51
52 __REG(CSCR_U(4)) = 0x0000dcf6; /* CS4: Network Controller */
53 __REG(CSCR_L(4)) = 0x444a4541;
54 __REG(CSCR_A(4)) = 0x44443302;
55
56 /* setup pins for UART1 */
57 mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
58 mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
59 mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
Magnus Liljab6b183c2008-08-03 21:43:37 +020060 mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
Sascha Hauercaebc952008-03-26 20:41:09 +010061
Magnus Liljaf9204e12008-04-20 10:38:12 +020062 /* SPI2 */
Magnus Lilja5276a352008-08-03 21:44:10 +020063 mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
64 mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
65 mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
66 mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
67 mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
68 mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
69 mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
Magnus Liljaf9204e12008-04-20 10:38:12 +020070
71 /* start SPI2 clock */
72 __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
73
Fabio Estevam4e377312011-06-05 14:56:02 +000074 return 0;
75}
76
77int board_init(void)
78{
Magnus Lilja17c9de62008-04-20 10:35:03 +020079 gd->bd->bi_arch_number = MACH_TYPE_MX31LITE; /* board id for linux */
Sascha Hauercaebc952008-03-26 20:41:09 +010080 gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */
81
82 return 0;
83}
84
85int checkboard (void)
86{
87 printf("Board: i.MX31 Litekit\n");
88 return 0;
89}
Ben Warren736fead2009-07-20 22:01:11 -070090
91int board_eth_init(bd_t *bis)
92{
93 int rc = 0;
94#ifdef CONFIG_SMC911X
95 rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
96#endif
97 return rc;
98}