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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Timur Tabic59e1b42010-06-14 15:28:24 -05002/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00003 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05004 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
5 * Timur Tabi <timur@freescale.com>
Timur Tabic59e1b42010-06-14 15:28:24 -05006 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#include "../board/freescale/common/ics307_clk.h"
12
Matthew McClintockaf253602012-05-18 06:04:17 +000013#ifdef CONFIG_SDCARD
Ying Zhang7c8eea52013-08-16 15:16:12 +080014#define CONFIG_SPL_FLUSH_IMAGE
15#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang7c8eea52013-08-16 15:16:12 +080016#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080017#define CONFIG_SPL_PAD_TO 0x20000
18#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053019#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080020#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
21#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080022#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080023#define CONFIG_SYS_MPC85XX_NO_RESETVEC
24#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
25#define CONFIG_SPL_MMC_BOOT
26#ifdef CONFIG_SPL_BUILD
27#define CONFIG_SPL_COMMON_INIT_DDR
28#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000029#endif
30
31#ifdef CONFIG_SPIFLASH
Ying Zhang382ce7e2013-08-16 15:16:14 +080032#define CONFIG_SPL_SPI_FLASH_MINIMAL
33#define CONFIG_SPL_FLUSH_IMAGE
34#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang382ce7e2013-08-16 15:16:14 +080035#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080036#define CONFIG_SPL_PAD_TO 0x20000
37#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053038#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080039#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
40#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080041#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080042#define CONFIG_SYS_MPC85XX_NO_RESETVEC
43#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
44#define CONFIG_SPL_SPI_BOOT
45#ifdef CONFIG_SPL_BUILD
46#define CONFIG_SPL_COMMON_INIT_DDR
47#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000048#endif
49
Matthew McClintockf45210d2013-02-18 10:02:19 +000050#define CONFIG_NAND_FSL_ELBC
York Sun9407c3f2013-12-17 11:21:08 -080051#define CONFIG_SYS_NAND_MAX_ECCPOS 56
52#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockf45210d2013-02-18 10:02:19 +000053
54#ifdef CONFIG_NAND
Ying Zhang5d97fe22013-08-16 15:16:16 +080055#ifdef CONFIG_TPL_BUILD
56#define CONFIG_SPL_NAND_BOOT
57#define CONFIG_SPL_FLUSH_IMAGE
Simon Glass989e1ce2016-09-12 23:18:45 -060058#define CONFIG_SPL_NAND_INIT
Ying Zhang5d97fe22013-08-16 15:16:16 +080059#define CONFIG_SPL_COMMON_INIT_DDR
60#define CONFIG_SPL_MAX_SIZE (128 << 10)
Tom Rinia6d68122019-01-22 17:09:24 -050061#define CONFIG_TPL_TEXT_BASE 0xf8f81000
Ying Zhang5d97fe22013-08-16 15:16:16 +080062#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053063#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang5d97fe22013-08-16 15:16:16 +080064#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
65#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
66#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
67#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +000068#define CONFIG_SPL_INIT_MINIMAL
Matthew McClintockf45210d2013-02-18 10:02:19 +000069#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang5d97fe22013-08-16 15:16:16 +080070#define CONFIG_SPL_TEXT_BASE 0xff800000
71#define CONFIG_SPL_MAX_SIZE 4096
72#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
73#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
74#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
75#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
76#endif
77#define CONFIG_SPL_PAD_TO 0x20000
78#define CONFIG_TPL_PAD_TO 0x20000
79#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Ying Zhang5d97fe22013-08-16 15:16:16 +080080#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockf45210d2013-02-18 10:02:19 +000081#endif
82
Timur Tabic59e1b42010-06-14 15:28:24 -050083/* High Level Configuration Options */
Timur Tabic59e1b42010-06-14 15:28:24 -050084
Kumar Gala7a577fd2011-01-12 02:48:53 -060085#ifndef CONFIG_RESET_VECTOR_ADDRESS
86#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
87#endif
88
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040089#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
90#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
91#define CONFIG_PCIE3 /* PCIE controller 3 (ULI bridge) */
Timur Tabic59e1b42010-06-14 15:28:24 -050092#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
93#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
94#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
95
Timur Tabic59e1b42010-06-14 15:28:24 -050096#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -050097
98#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -050099#define CONFIG_ADDR_MAP
100#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800101#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500102
Timur Tabic59e1b42010-06-14 15:28:24 -0500103#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
104#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
105#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
106
107/*
108 * These can be toggled for performance analysis, otherwise use default.
109 */
110#define CONFIG_L2_CACHE
111#define CONFIG_BTB
112
113#define CONFIG_SYS_MEMTEST_START 0x00000000
114#define CONFIG_SYS_MEMTEST_END 0x7fffffff
115
Timur Tabie46fedf2011-08-04 18:03:41 -0500116#define CONFIG_SYS_CCSRBAR 0xffe00000
117#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500118
Matthew McClintockf45210d2013-02-18 10:02:19 +0000119/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
120 SPL code*/
121#ifdef CONFIG_SPL_BUILD
122#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
123#endif
124
Timur Tabic59e1b42010-06-14 15:28:24 -0500125/* DDR Setup */
126#define CONFIG_DDR_SPD
127#define CONFIG_VERY_BIG_RAM
Timur Tabic59e1b42010-06-14 15:28:24 -0500128
129#ifdef CONFIG_DDR_ECC
130#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
131#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
132#endif
133
134#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
135#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
136
Timur Tabic59e1b42010-06-14 15:28:24 -0500137#define CONFIG_DIMM_SLOTS_PER_CTLR 1
138#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
139
140/* I2C addresses of SPD EEPROMs */
141#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600142#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500143
Matthew McClintockf45210d2013-02-18 10:02:19 +0000144/* These are used when DDR doesn't use SPD. */
145#define CONFIG_SYS_SDRAM_SIZE 2048
146#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
147#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
148#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
149#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
150#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
151#define CONFIG_SYS_DDR_TIMING_3 0x00010000
152#define CONFIG_SYS_DDR_TIMING_0 0x40110104
153#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
154#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
155#define CONFIG_SYS_DDR_MODE_1 0x00441221
156#define CONFIG_SYS_DDR_MODE_2 0x00000000
157#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
158#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
159#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
160#define CONFIG_SYS_DDR_CONTROL 0xc7000008
161#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
162#define CONFIG_SYS_DDR_TIMING_4 0x00220001
163#define CONFIG_SYS_DDR_TIMING_5 0x02401400
164#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
165#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
166
Timur Tabic59e1b42010-06-14 15:28:24 -0500167/*
168 * Memory map
169 *
170 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
171 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
172 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
173 *
174 * Localbus cacheable (TBD)
175 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
176 *
177 * Localbus non-cacheable
178 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
179 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000180 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500181 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
182 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
183 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
184 */
185
186/*
187 * Local Bus Definitions
188 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000189#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800190#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000191#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800192#else
193#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
194#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500195
196#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000197 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500198#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
199
Matthew McClintockf45210d2013-02-18 10:02:19 +0000200#ifdef CONFIG_NAND
201#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
202#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
203#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500204#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
205#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000206#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500207
Matthew McClintockf45210d2013-02-18 10:02:19 +0000208#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500209#define CONFIG_SYS_FLASH_QUIET_TEST
210#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
211
Matthew McClintockf45210d2013-02-18 10:02:19 +0000212#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500213#define CONFIG_SYS_MAX_FLASH_SECT 1024
214
Matthew McClintockf45210d2013-02-18 10:02:19 +0000215#ifndef CONFIG_SYS_MONITOR_BASE
Tom Rinia6d68122019-01-22 17:09:24 -0500216#ifdef CONFIG_TPL_BUILD
217#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE
218#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000219#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
220#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200221#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000222#endif
223#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500224
Timur Tabic59e1b42010-06-14 15:28:24 -0500225#define CONFIG_SYS_FLASH_EMPTY_INFO
226
Matthew McClintockf45210d2013-02-18 10:02:19 +0000227/* Nand Flash */
228#if defined(CONFIG_NAND_FSL_ELBC)
229#define CONFIG_SYS_NAND_BASE 0xff800000
230#ifdef CONFIG_PHYS_64BIT
231#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
232#else
233#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
234#endif
235
Ying Zhang5d97fe22013-08-16 15:16:16 +0800236#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockf45210d2013-02-18 10:02:19 +0000237#define CONFIG_SYS_MAX_NAND_DEVICE 1
Ying Zhang5d97fe22013-08-16 15:16:16 +0800238#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000239#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
240
241/* NAND flash config */
242#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
243 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
244 | BR_PS_8 /* Port Size = 8 bit */ \
245 | BR_MS_FCM /* MSEL = FCM */ \
246 | BR_V) /* valid */
247#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
248 | OR_FCM_PGS /* Large Page*/ \
249 | OR_FCM_CSCT \
250 | OR_FCM_CST \
251 | OR_FCM_CHT \
252 | OR_FCM_SCY_1 \
253 | OR_FCM_TRLX \
254 | OR_FCM_EHTR)
255#ifdef CONFIG_NAND
256#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
257#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
258#else
259#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
260#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
261#endif
262
263#endif /* CONFIG_NAND_FSL_ELBC */
264
Timur Tabia2d12f82010-07-21 16:56:19 -0500265#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500266
267#define CONFIG_FSL_NGPIXIS
268#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800269#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500270#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800271#else
272#define PIXIS_BASE_PHYS PIXIS_BASE
273#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500274
275#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
276#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
277
278#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800279#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500280#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000281#define PIXIS_SPD 0x07
282#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800283#define PIXIS_ELBC_SPI_MASK 0xc0
284#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500285
286#define CONFIG_SYS_INIT_RAM_LOCK
287#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200288#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500289
Timur Tabic59e1b42010-06-14 15:28:24 -0500290#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200291 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500292#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
293
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530294#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800295#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500296
297/*
Ying Zhang7c8eea52013-08-16 15:16:12 +0800298 * Config the L2 Cache as L2 SRAM
299*/
300#if defined(CONFIG_SPL_BUILD)
Ying Zhang382ce7e2013-08-16 15:16:14 +0800301#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800302#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
303#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
304#define CONFIG_SYS_L2_SIZE (256 << 10)
305#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
306#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang27585bd2014-01-24 15:50:08 +0800307#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang27585bd2014-01-24 15:50:08 +0800308#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
309#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800310#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800311#elif defined(CONFIG_NAND)
312#ifdef CONFIG_TPL_BUILD
313#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
314#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
315#define CONFIG_SYS_L2_SIZE (256 << 10)
316#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
317#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
318#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
319#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
320#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
321#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
322#else
323#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
324#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
325#define CONFIG_SYS_L2_SIZE (256 << 10)
326#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
327#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
328#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
329#endif
Ying Zhang7c8eea52013-08-16 15:16:12 +0800330#endif
331#endif
332
333/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500334 * Serial Port
335 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500336#define CONFIG_SYS_NS16550_SERIAL
337#define CONFIG_SYS_NS16550_REG_SIZE 1
338#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800339#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000340#define CONFIG_NS16550_MIN_FUNCTIONS
341#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500342
343#define CONFIG_SYS_BAUDRATE_TABLE \
344 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
345
346#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
347#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
348
Timur Tabic59e1b42010-06-14 15:28:24 -0500349/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500350
Timur Tabid5e01e42010-09-24 01:25:53 +0200351#ifdef CONFIG_FSL_DIU_FB
352#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
Timur Tabid5e01e42010-09-24 01:25:53 +0200353#define CONFIG_VIDEO_LOGO
354#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500355#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
356/*
357 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
358 * disable empty flash sector detection, which is I/O-intensive.
359 */
360#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500361#endif
362
Jiang Yutang218a7582011-01-24 18:21:19 +0800363#ifdef CONFIG_ATI
364#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
Jiang Yutang218a7582011-01-24 18:21:19 +0800365#define CONFIG_BIOSEMU
Jiang Yutang218a7582011-01-24 18:21:19 +0800366#define CONFIG_ATI_RADEON_FB
367#define CONFIG_VIDEO_LOGO
368#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Jiang Yutang218a7582011-01-24 18:21:19 +0800369#endif
370
Timur Tabic59e1b42010-06-14 15:28:24 -0500371/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200372#define CONFIG_SYS_I2C
373#define CONFIG_SYS_I2C_FSL
374#define CONFIG_SYS_FSL_I2C_SPEED 400000
375#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
376#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
377#define CONFIG_SYS_FSL_I2C2_SPEED 400000
378#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
379#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabic59e1b42010-06-14 15:28:24 -0500380#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabic59e1b42010-06-14 15:28:24 -0500381
382/*
383 * I2C2 EEPROM
384 */
385#define CONFIG_ID_EEPROM
386#define CONFIG_SYS_I2C_EEPROM_NXID
387#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
388#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
389#define CONFIG_SYS_EEPROM_BUS_NUM 1
390
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800391/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500392 * General PCI
393 * Memory space is mapped 1-1, but I/O space must start from 0.
394 */
395
396/* controller 1, Slot 2, tgtid 1, Base address a000 */
397#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800398#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500399#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
400#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800401#else
402#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
403#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
404#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500405#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
406#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
407#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800408#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500409#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800410#else
411#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
412#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500413#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
414
415/* controller 2, direct to uli, tgtid 2, Base address 9000 */
416#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800417#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500418#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
419#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800420#else
421#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
422#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
423#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500424#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
425#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
426#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800427#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500428#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800429#else
430#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
431#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500432#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
433
434/* controller 3, Slot 1, tgtid 3, Base address b000 */
435#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800436#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500437#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
438#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800439#else
440#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
441#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
442#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500443#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
444#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
445#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800446#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500447#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800448#else
449#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
450#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500451#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
452
453#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000454#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabic59e1b42010-06-14 15:28:24 -0500455#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
456#endif
457
458/* SATA */
Zang Roy-R619119760b272012-11-26 00:05:38 +0000459#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500460
461#define CONFIG_SYS_SATA_MAX_DEVICE 2
462#define CONFIG_SATA1
463#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
464#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
465#define CONFIG_SATA2
466#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
467#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
468
469#ifdef CONFIG_FSL_SATA
470#define CONFIG_LBA48
Timur Tabic59e1b42010-06-14 15:28:24 -0500471#endif
472
Timur Tabic59e1b42010-06-14 15:28:24 -0500473#ifdef CONFIG_MMC
Timur Tabic59e1b42010-06-14 15:28:24 -0500474#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
475#endif
476
Timur Tabic59e1b42010-06-14 15:28:24 -0500477#ifdef CONFIG_TSEC_ENET
478
479#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500480
Timur Tabic59e1b42010-06-14 15:28:24 -0500481#define CONFIG_TSEC1 1
482#define CONFIG_TSEC1_NAME "eTSEC1"
483#define CONFIG_TSEC2 1
484#define CONFIG_TSEC2_NAME "eTSEC2"
485
486#define TSEC1_PHY_ADDR 1
487#define TSEC2_PHY_ADDR 2
488
489#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
490#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
491
492#define TSEC1_PHYIDX 0
493#define TSEC2_PHYIDX 0
494
495#define CONFIG_ETHPRIME "eTSEC1"
Timur Tabic59e1b42010-06-14 15:28:24 -0500496#endif
497
498/*
Yangbo Lu94b383e2014-10-16 10:58:55 +0800499 * Dynamic MTD Partition support with mtdparts
500 */
Yangbo Lu94b383e2014-10-16 10:58:55 +0800501
502/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500503 * Environment
504 */
Ying Zhang382ce7e2013-08-16 15:16:14 +0800505#ifdef CONFIG_SPIFLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000506#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
507#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
508#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhang7c8eea52013-08-16 15:16:12 +0800509#elif defined(CONFIG_SDCARD)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800510#define CONFIG_FSL_FIXED_MMC_LOCATION
Timur Tabic59e1b42010-06-14 15:28:24 -0500511#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000512#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000513#elif defined(CONFIG_NAND)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800514#ifdef CONFIG_TPL_BUILD
515#define CONFIG_ENV_SIZE 0x2000
516#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
517#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000518#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800519#endif
Ying Zhang5d97fe22013-08-16 15:16:16 +0800520#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockaf253602012-05-18 06:04:17 +0000521#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000522#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000523#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
524#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000525#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000526#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Matthew McClintockaf253602012-05-18 06:04:17 +0000527#define CONFIG_ENV_SIZE 0x2000
528#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
529#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500530
531#define CONFIG_LOADS_ECHO
532#define CONFIG_SYS_LOADS_BAUD_CHANGE
533
534/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500535 * USB
536 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000537#define CONFIG_HAS_FSL_DR_USB
538#ifdef CONFIG_HAS_FSL_DR_USB
Tom Rini8850c5d2017-05-12 22:33:27 -0400539#ifdef CONFIG_USB_EHCI_HCD
Timur Tabic59e1b42010-06-14 15:28:24 -0500540#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
541#define CONFIG_USB_EHCI_FSL
Timur Tabic59e1b42010-06-14 15:28:24 -0500542#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000543#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500544
545/*
546 * Miscellaneous configurable options
547 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500548#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabic59e1b42010-06-14 15:28:24 -0500549
550/*
551 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500552 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500553 * the maximum mapped by the Linux kernel during initialization.
554 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500555#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
556#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500557
Timur Tabic59e1b42010-06-14 15:28:24 -0500558#ifdef CONFIG_CMD_KGDB
559#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabic59e1b42010-06-14 15:28:24 -0500560#endif
561
562/*
563 * Environment Configuration
564 */
565
Mario Six5bc05432018-03-28 14:38:20 +0200566#define CONFIG_HOSTNAME "p1022ds"
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000567#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000568#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500569#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
570
571#define CONFIG_LOADADDR 1000000
572
Timur Tabi84e34b62012-05-04 12:21:29 +0000573#define CONFIG_EXTRA_ENV_SETTINGS \
574 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200575 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
576 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000577 "tftpflash=tftpboot $loadaddr $uboot && " \
578 "protect off $ubootaddr +$filesize && " \
579 "erase $ubootaddr +$filesize && " \
580 "cp.b $loadaddr $ubootaddr $filesize && " \
581 "protect on $ubootaddr +$filesize && " \
582 "cmp.b $loadaddr $ubootaddr $filesize\0" \
583 "consoledev=ttyS0\0" \
584 "ramdiskaddr=2000000\0" \
585 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500586 "fdtaddr=1e00000\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000587 "fdtfile=p1022ds.dtb\0" \
588 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500589 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500590
591#define CONFIG_HDBOOT \
592 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000593 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500594 "tftp $loadaddr $bootfile;" \
595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr - $fdtaddr"
597
598#define CONFIG_NFSBOOTCOMMAND \
599 "setenv bootargs root=/dev/nfs rw " \
600 "nfsroot=$serverip:$rootpath " \
601 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000602 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500603 "tftp $loadaddr $bootfile;" \
604 "tftp $fdtaddr $fdtfile;" \
605 "bootm $loadaddr - $fdtaddr"
606
607#define CONFIG_RAMBOOTCOMMAND \
608 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000609 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500610 "tftp $ramdiskaddr $ramdiskfile;" \
611 "tftp $loadaddr $bootfile;" \
612 "tftp $fdtaddr $fdtfile;" \
613 "bootm $loadaddr $ramdiskaddr $fdtaddr"
614
615#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
616
617#endif