blob: 800d2d14765db396c547cc76b2bc196dfd0bb820 [file] [log] [blame]
Stefan Roesef8d25d72015-01-19 11:33:40 +01001/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#ifndef __DDR3_AXP_CONFIG_H
8#define __DDR3_AXP_CONFIG_H
9
10/*
11 * DDR3_LOG_LEVEL Information
12 *
13 * Level 0: Provides an error code in a case of failure, RL, WL errors
14 * and other algorithm failure
15 * Level 1: Provides the D-Unit setup (SPD/Static configuration)
16 * Level 2: Provides the windows margin as a results of DQS centeralization
17 * Level 3: Provides the windows margin of each DQ as a results of DQS
18 * centeralization
19 */
20#ifdef CONFIG_DDR_LOG_LEVEL
21#define DDR3_LOG_LEVEL CONFIG_DDR_LOG_LEVEL
22#else
23#define DDR3_LOG_LEVEL 0
24#endif
25
26#define DDR3_PBS 1
27
28/* This flag allows the execution of SW WL/RL upon HW failure */
29#define DDR3_RUN_SW_WHEN_HW_FAIL 1
30
31/*
32 * General Configurations
33 *
34 * The following parameters are required for proper setup:
35 *
36 * DDR_TARGET_FABRIC - Set desired fabric configuration
37 * (for sample@Reset fabfreq parameter)
38 * DRAM_ECC - Set ECC support 1/0
39 * BUS_WIDTH - 64/32 bit
40 * CONFIG_SPD_EEPROM - Enables auto detection of DIMMs and their timing values
41 * DQS_CLK_ALIGNED - Set this if CLK and DQS signals are aligned on board
42 * MIXED_DIMM_STATIC - Mixed DIMM + On board devices support (ODT registers
43 * values are taken statically)
44 * DDR3_TRAINING_DEBUG - Debug prints of internal code
45 */
46#define DDR_TARGET_FABRIC 5
47#define DRAM_ECC 0
48
49#ifdef MV_DDR_32BIT
50#define BUS_WIDTH 32
51#else
52#define BUS_WIDTH 64
53#endif
54
55#undef DQS_CLK_ALIGNED
56#undef MIXED_DIMM_STATIC
57#define DDR3_TRAINING_DEBUG 0
58#define REG_DIMM_SKIP_WL 0
59
60/* Marvell boards specific configurations */
61#if defined(DB_78X60_PCAC)
62#undef CONFIG_SPD_EEPROM
63#define STATIC_TRAINING
64#endif
65
66#if defined(DB_78X60_AMC)
67#undef CONFIG_SPD_EEPROM
68#undef DRAM_ECC
69#define DRAM_ECC 1
70#endif
71
72#ifdef CONFIG_SPD_EEPROM
73/*
74 * DIMM support parameters:
75 * DRAM_2T - Set Desired 2T Mode - 0 - 1T, 0x1 - 2T, 0x2 - 3T
76 * DIMM_CS_BITMAP - bitmap representing the optional CS in DIMMs
77 * (0xF=CS0+CS1+CS2+CS3, 0xC=CS2+CS3...)
78 */
79#define DRAM_2T 0x0
80#define DIMM_CS_BITMAP 0xF
81#define DUNIT_SPD
82#endif
83
84#ifdef DRAM_ECC
85/*
86 * ECC support parameters:
87 *
88 * U_BOOT_START_ADDR, U_BOOT_SCRUB_SIZE - relevant when using ECC and need
89 * to configure the scrubbing area
90 */
91#define TRAINING_SIZE 0x20000
92#define U_BOOT_START_ADDR 0
93#define U_BOOT_SCRUB_SIZE 0x1000000 /* TRAINING_SIZE */
94#endif
95
96/*
97 * Registered DIMM Support - In case registered DIMM is attached,
98 * please supply the following values:
99 * (see JEDEC - JESD82-29A "Definition of the SSTE32882 Registering Clock
100 * Driver with Parity and Quad Chip
101 * Selects for DDR3/DDR3L/DDR3U RDIMM 1.5 V/1.35 V/1.25 V Applications")
102 * RC0: Global Features Control Word
103 * RC1: Clock Driver Enable Control Word
104 * RC2: Timing Control Word
105 * RC3-RC5 - taken from SPD
106 * RC8: Additional IBT Setting Control Word
107 * RC9: Power Saving Settings Control Word
108 * RC10: Encoding for RDIMM Operating Speed
109 * RC11: Operating Voltage VDD and VREFCA Control Word
110 */
111#define RDIMM_RC0 0
112#define RDIMM_RC1 0
113#define RDIMM_RC2 0
114#define RDIMM_RC8 0
115#define RDIMM_RC9 0
116#define RDIMM_RC10 0x2
117#define RDIMM_RC11 0x0
118
119#if defined(MIXED_DIMM_STATIC) || !defined(CONFIG_SPD_EEPROM)
120#define DUNIT_STATIC
121#endif
122
123#if defined(MIXED_DIMM_STATIC) || defined(CONFIG_SPD_EEPROM)
124/*
125 * This flag allows the user to change the dram refresh cycle in ps,
126 * only in case of SPD or MIX DIMM topology
127 */
128#define TREFI_USER_EN
129
130#ifdef TREFI_USER_EN
131#define TREFI_USER 3900000
132#endif
133#endif
134
135#ifdef CONFIG_SPD_EEPROM
136/*
137 * AUTO_DETECTION_SUPPORT - relevant ONLY for Marvell DB boards.
138 * Enables I2C auto detection different options
139 */
140#if defined(CONFIG_DB_88F78X60) || defined(CONFIG_DB_88F78X60_REV2) || \
141 defined(CONFIG_DB_784MP_GP)
142#define AUTO_DETECTION_SUPPORT
143#endif
144#endif
145
146#endif /* __DDR3_AXP_CONFIG_H */