blob: b1519635028dad2715f4d844b2df78638ebe7a81 [file] [log] [blame]
Shengzhou Liuaba80042014-11-24 17:11:55 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T1024/T1023 QDS board configuration file
9 */
10
11#ifndef __T1024QDS_H
12#define __T1024QDS_H
13
14/* High Level Configuration Options */
Shengzhou Liuaba80042014-11-24 17:11:55 +080015#define CONFIG_DISPLAY_BOARDINFO
16#define CONFIG_BOOKE
17#define CONFIG_E500 /* BOOKE e500 family */
18#define CONFIG_E500MC /* BOOKE e500mc family */
19#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
20#define CONFIG_MP /* support multiple processors */
21#define CONFIG_PHYS_64BIT
22#define CONFIG_ENABLE_36BIT_PHYS
23
24#ifdef CONFIG_PHYS_64BIT
25#define CONFIG_ADDR_MAP 1
26#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
27#endif
28
29#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
30#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
31#define CONFIG_FSL_IFC /* Enable IFC Support */
32
33#define CONFIG_FSL_LAW /* Use common FSL init code */
34#define CONFIG_ENV_OVERWRITE
35
36#define CONFIG_DEEP_SLEEP
tang yuantian2c537642014-12-18 09:55:07 +080037#if defined(CONFIG_DEEP_SLEEP)
Shengzhou Liuaba80042014-11-24 17:11:55 +080038#define CONFIG_SILENT_CONSOLE
tang yuantian2c537642014-12-18 09:55:07 +080039#define CONFIG_BOARD_EARLY_INIT_F
40#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +080041
Aneesh Bansalef6c55a2016-01-22 16:37:22 +053042#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
43
Shengzhou Liuaba80042014-11-24 17:11:55 +080044#ifdef CONFIG_RAMBOOT_PBL
45#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
46#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xqds/t1024_rcw.cfg
47#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48#define CONFIG_SPL_ENV_SUPPORT
49#define CONFIG_SPL_SERIAL_SUPPORT
50#define CONFIG_SPL_FLUSH_IMAGE
51#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
52#define CONFIG_SPL_LIBGENERIC_SUPPORT
53#define CONFIG_SPL_LIBCOMMON_SUPPORT
54#define CONFIG_SPL_I2C_SUPPORT
55#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
56#define CONFIG_FSL_LAW /* Use common FSL init code */
57#define CONFIG_SYS_TEXT_BASE 0x00201000
58#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
59#define CONFIG_SPL_PAD_TO 0x40000
60#define CONFIG_SPL_MAX_SIZE 0x28000
61#define RESET_VECTOR_OFFSET 0x27FFC
62#define BOOT_PAGE_OFFSET 0x27000
63#ifdef CONFIG_SPL_BUILD
64#define CONFIG_SPL_SKIP_RELOCATE
65#define CONFIG_SPL_COMMON_INIT_DDR
66#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
67#define CONFIG_SYS_NO_FLASH
68#endif
69
70#ifdef CONFIG_NAND
71#define CONFIG_SPL_NAND_SUPPORT
72#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
73#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
74#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
75#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
76#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
77#define CONFIG_SPL_NAND_BOOT
78#endif
79
80#ifdef CONFIG_SPIFLASH
81#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
82#define CONFIG_SPL_SPI_SUPPORT
83#define CONFIG_SPL_SPI_FLASH_SUPPORT
84#define CONFIG_SPL_SPI_FLASH_MINIMAL
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
86#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
87#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
88#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
89#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90#ifndef CONFIG_SPL_BUILD
91#define CONFIG_SYS_MPC85XX_NO_RESETVEC
92#endif
93#define CONFIG_SPL_SPI_BOOT
94#endif
95
96#ifdef CONFIG_SDCARD
97#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
98#define CONFIG_SPL_MMC_SUPPORT
99#define CONFIG_SPL_MMC_MINIMAL
100#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
101#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
102#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
103#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
104#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
105#ifndef CONFIG_SPL_BUILD
106#define CONFIG_SYS_MPC85XX_NO_RESETVEC
107#endif
108#define CONFIG_SPL_MMC_BOOT
109#endif
110
111#endif /* CONFIG_RAMBOOT_PBL */
112
113#ifndef CONFIG_SYS_TEXT_BASE
114#define CONFIG_SYS_TEXT_BASE 0xeff40000
115#endif
116
117#ifndef CONFIG_RESET_VECTOR_ADDRESS
118#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
119#endif
120
121#ifndef CONFIG_SYS_NO_FLASH
122#define CONFIG_FLASH_CFI_DRIVER
123#define CONFIG_SYS_FLASH_CFI
124#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
125#endif
126
127/* PCIe Boot - Master */
128#define CONFIG_SRIO_PCIE_BOOT_MASTER
129/*
130 * for slave u-boot IMAGE instored in master memory space,
131 * PHYS must be aligned based on the SIZE
132 */
133#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
134#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
135#ifdef CONFIG_PHYS_64BIT
136#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
137#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
138#else
139#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
140#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
141#endif
142/*
143 * for slave UCODE and ENV instored in master memory space,
144 * PHYS must be aligned based on the SIZE
145 */
146#ifdef CONFIG_PHYS_64BIT
147#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
148#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
149#else
150#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
151#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
152#endif
153#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
154/* slave core release by master*/
155#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
156#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
157
158/* PCIe Boot - Slave */
159#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
160#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
161#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
162 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
163/* Set 1M boot space for PCIe boot */
164#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
165#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
166 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
167#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
168#define CONFIG_SYS_NO_FLASH
169#endif
170
171#if defined(CONFIG_SPIFLASH)
172#define CONFIG_SYS_EXTRA_ENV_RELOC
173#define CONFIG_ENV_IS_IN_SPI_FLASH
174#define CONFIG_ENV_SPI_BUS 0
175#define CONFIG_ENV_SPI_CS 0
176#define CONFIG_ENV_SPI_MAX_HZ 10000000
177#define CONFIG_ENV_SPI_MODE 0
178#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
179#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
180#define CONFIG_ENV_SECT_SIZE 0x10000
181#elif defined(CONFIG_SDCARD)
182#define CONFIG_SYS_EXTRA_ENV_RELOC
183#define CONFIG_ENV_IS_IN_MMC
184#define CONFIG_SYS_MMC_ENV_DEV 0
185#define CONFIG_ENV_SIZE 0x2000
186#define CONFIG_ENV_OFFSET (512 * 0x800)
187#elif defined(CONFIG_NAND)
188#define CONFIG_SYS_EXTRA_ENV_RELOC
189#define CONFIG_ENV_IS_IN_NAND
190#define CONFIG_ENV_SIZE 0x2000
191#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
192#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
193#define CONFIG_ENV_IS_IN_REMOTE
194#define CONFIG_ENV_ADDR 0xffe20000
195#define CONFIG_ENV_SIZE 0x2000
196#elif defined(CONFIG_ENV_IS_NOWHERE)
197#define CONFIG_ENV_SIZE 0x2000
198#else
199#define CONFIG_ENV_IS_IN_FLASH
200#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
201#define CONFIG_ENV_SIZE 0x2000
202#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
203#endif
204
Shengzhou Liuaba80042014-11-24 17:11:55 +0800205#ifndef __ASSEMBLY__
206unsigned long get_board_sys_clk(void);
207unsigned long get_board_ddr_clk(void);
208#endif
209
210#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
211#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
212
213/*
214 * These can be toggled for performance analysis, otherwise use default.
215 */
216#define CONFIG_SYS_CACHE_STASHING
217#define CONFIG_BACKSIDE_L2_CACHE
218#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
219#define CONFIG_BTB /* toggle branch predition */
220#define CONFIG_DDR_ECC
221#ifdef CONFIG_DDR_ECC
222#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
223#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
224#endif
225
226#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
227#define CONFIG_SYS_MEMTEST_END 0x00400000
228#define CONFIG_SYS_ALT_MEMTEST
229#define CONFIG_PANIC_HANG /* do not reset board on panic */
230
231/*
232 * Config the L3 Cache as L3 SRAM
233 */
234#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
235#define CONFIG_SYS_L3_SIZE (256 << 10)
236#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
237#ifdef CONFIG_RAMBOOT_PBL
238#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
239#endif
240#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
241#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
242#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
243#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
244
245#ifdef CONFIG_PHYS_64BIT
246#define CONFIG_SYS_DCSRBAR 0xf0000000
247#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
248#endif
249
250/* EEPROM */
251#define CONFIG_ID_EEPROM
252#define CONFIG_SYS_I2C_EEPROM_NXID
253#define CONFIG_SYS_EEPROM_BUS_NUM 0
254#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
255#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
256#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
257#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
258
259/*
260 * DDR Setup
261 */
262#define CONFIG_VERY_BIG_RAM
263#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
264#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
265#define CONFIG_DIMM_SLOTS_PER_CTLR 1
266#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
267#define CONFIG_DDR_SPD
268#ifndef CONFIG_SYS_FSL_DDR4
269#define CONFIG_SYS_FSL_DDR3
270#endif
271
272#define CONFIG_SYS_SPD_BUS_NUM 0
273#define SPD_EEPROM_ADDRESS 0x51
274
275#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
276
277/*
278 * IFC Definitions
279 */
280#define CONFIG_SYS_FLASH_BASE 0xe0000000
281#ifdef CONFIG_PHYS_64BIT
282#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
283#else
284#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
285#endif
286
287#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
288#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
289 + 0x8000000) | \
290 CSPR_PORT_SIZE_16 | \
291 CSPR_MSEL_NOR | \
292 CSPR_V)
293#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
294#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
295 CSPR_PORT_SIZE_16 | \
296 CSPR_MSEL_NOR | \
297 CSPR_V)
298#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
299/* NOR Flash Timing Params */
300#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
301#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
302 FTIM0_NOR_TEADC(0x5) | \
303 FTIM0_NOR_TEAHC(0x5))
304#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
305 FTIM1_NOR_TRAD_NOR(0x1A) |\
306 FTIM1_NOR_TSEQRAD_NOR(0x13))
307#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
308 FTIM2_NOR_TCH(0x4) | \
309 FTIM2_NOR_TWPH(0x0E) | \
310 FTIM2_NOR_TWP(0x1c))
311#define CONFIG_SYS_NOR_FTIM3 0x0
312
313#define CONFIG_SYS_FLASH_QUIET_TEST
314#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
315
316#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
317#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
318#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
319#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
320
321#define CONFIG_SYS_FLASH_EMPTY_INFO
322#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
323 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
324#define CONFIG_FSL_QIXIS /* use common QIXIS code */
325#define QIXIS_BASE 0xffdf0000
326#ifdef CONFIG_PHYS_64BIT
327#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
328#else
329#define QIXIS_BASE_PHYS QIXIS_BASE
330#endif
331#define QIXIS_LBMAP_SWITCH 0x06
332#define QIXIS_LBMAP_MASK 0x0f
333#define QIXIS_LBMAP_SHIFT 0
334#define QIXIS_LBMAP_DFLTBANK 0x00
335#define QIXIS_LBMAP_ALTBANK 0x04
336#define QIXIS_RST_CTL_RESET 0x31
337#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
338#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
339#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
340#define QIXIS_RST_FORCE_MEM 0x01
341
342#define CONFIG_SYS_CSPR3_EXT (0xf)
343#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
344 | CSPR_PORT_SIZE_8 \
345 | CSPR_MSEL_GPCM \
346 | CSPR_V)
347#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
348#define CONFIG_SYS_CSOR3 0x0
349/* QIXIS Timing parameters for IFC CS3 */
350#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
351 FTIM0_GPCM_TEADC(0x0e) | \
352 FTIM0_GPCM_TEAHC(0x0e))
353#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
354 FTIM1_GPCM_TRAD(0x3f))
355#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
356 FTIM2_GPCM_TCH(0x8) | \
357 FTIM2_GPCM_TWP(0x1f))
358#define CONFIG_SYS_CS3_FTIM3 0x0
359
360#define CONFIG_NAND_FSL_IFC
361#define CONFIG_SYS_NAND_BASE 0xff800000
362#ifdef CONFIG_PHYS_64BIT
363#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
364#else
365#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
366#endif
367#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
368#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
369 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
370 | CSPR_MSEL_NAND /* MSEL = NAND */ \
371 | CSPR_V)
372#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
373
374#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
375 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
376 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
377 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
378 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
379 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
380 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
381
382#define CONFIG_SYS_NAND_ONFI_DETECTION
383
384/* ONFI NAND Flash mode0 Timing Params */
385#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
386 FTIM0_NAND_TWP(0x18) | \
387 FTIM0_NAND_TWCHT(0x07) | \
388 FTIM0_NAND_TWH(0x0a))
389#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
390 FTIM1_NAND_TWBE(0x39) | \
391 FTIM1_NAND_TRR(0x0e) | \
392 FTIM1_NAND_TRP(0x18))
393#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
394 FTIM2_NAND_TREH(0x0a) | \
395 FTIM2_NAND_TWHRE(0x1e))
396#define CONFIG_SYS_NAND_FTIM3 0x0
397
398#define CONFIG_SYS_NAND_DDR_LAW 11
399#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
400#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800401#define CONFIG_CMD_NAND
402
403#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
404
405#if defined(CONFIG_NAND)
406#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
407#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
408#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
409#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
410#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
411#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
412#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
413#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
414#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
415#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
416#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
417#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
418#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
419#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
420#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
421#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
422#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
423#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
424#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
425#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
426#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
427#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
428#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
429#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
430#else
431#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
432#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
433#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
434#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
435#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
436#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
437#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
438#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
439#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
440#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
441#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
442#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
443#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
444#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
445#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
446#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
447#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
448#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
449#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
450#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
451#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
452#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
453#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
454#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
455#endif
456
457#ifdef CONFIG_SPL_BUILD
458#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
459#else
460#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
461#endif
462
463#if defined(CONFIG_RAMBOOT_PBL)
464#define CONFIG_SYS_RAMBOOT
465#endif
466
467#define CONFIG_BOARD_EARLY_INIT_R
468#define CONFIG_MISC_INIT_R
469
470#define CONFIG_HWCONFIG
471
472/* define to use L1 as initial stack */
473#define CONFIG_L1_INIT_RAM
474#define CONFIG_SYS_INIT_RAM_LOCK
475#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
476#ifdef CONFIG_PHYS_64BIT
477#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700478#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liuaba80042014-11-24 17:11:55 +0800479/* The assembler doesn't like typecast */
480#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
481 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
482 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
483#else
York Sunb3142e22015-08-17 13:31:51 -0700484#define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfe03c000 /* Initial L1 address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800485#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
486#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
487#endif
488#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
489
490#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
491 GENERATED_GBL_DATA_SIZE)
492#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
493
494#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
495#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
496
497/* Serial Port */
498#define CONFIG_CONS_INDEX 1
Shengzhou Liuaba80042014-11-24 17:11:55 +0800499#define CONFIG_SYS_NS16550_SERIAL
500#define CONFIG_SYS_NS16550_REG_SIZE 1
501#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
502
503#define CONFIG_SYS_BAUDRATE_TABLE \
504 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
505
506#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
507#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
508#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
509#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
510#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
511
Shengzhou Liuaba80042014-11-24 17:11:55 +0800512/* Video */
513#ifdef CONFIG_PPC_T1024 /* no DIU on T1023 */
514#define CONFIG_FSL_DIU_FB
515#ifdef CONFIG_FSL_DIU_FB
516#define CONFIG_FSL_DIU_CH7301
517#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
518#define CONFIG_VIDEO
519#define CONFIG_CMD_BMP
520#define CONFIG_CFB_CONSOLE
521#define CONFIG_VIDEO_SW_CURSOR
522#define CONFIG_VGA_AS_SINGLE_DEVICE
523#define CONFIG_VIDEO_LOGO
524#define CONFIG_VIDEO_BMP_LOGO
525#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
526/*
527 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
528 * disable empty flash sector detection, which is I/O-intensive.
529 */
530#undef CONFIG_SYS_FLASH_EMPTY_INFO
531#endif
532#endif
533
Shengzhou Liuaba80042014-11-24 17:11:55 +0800534/* I2C */
535#define CONFIG_SYS_I2C
536#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
537#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
538#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
539#define CONFIG_SYS_FSL_I2C2_SPEED 50000 /* I2C speed in Hz */
540#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
541#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
542#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
543
544#define I2C_MUX_PCA_ADDR 0x77
545#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800546#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
547#define I2C_RETIMER_ADDR 0x18
Shengzhou Liuaba80042014-11-24 17:11:55 +0800548
549/* I2C bus multiplexer */
550#define I2C_MUX_CH_DEFAULT 0x8
551#define I2C_MUX_CH_DIU 0xC
Shengzhou Liu10227aa2014-11-24 17:18:28 +0800552#define I2C_MUX_CH5 0xD
553#define I2C_MUX_CH7 0xF
Shengzhou Liuaba80042014-11-24 17:11:55 +0800554
555/* LDI/DVI Encoder for display */
556#define CONFIG_SYS_I2C_LDI_ADDR 0x38
557#define CONFIG_SYS_I2C_DVI_ADDR 0x75
558
559/*
560 * RTC configuration
561 */
562#define RTC
563#define CONFIG_RTC_DS3231 1
564#define CONFIG_SYS_I2C_RTC_ADDR 0x68
565
566/*
567 * eSPI - Enhanced SPI
568 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800569#ifndef CONFIG_SPL_BUILD
Shengzhou Liuaba80042014-11-24 17:11:55 +0800570#endif
Shengzhou Liuaba80042014-11-24 17:11:55 +0800571#define CONFIG_SPI_FLASH_BAR
572#define CONFIG_SF_DEFAULT_SPEED 10000000
573#define CONFIG_SF_DEFAULT_MODE 0
574
575/*
576 * General PCIe
577 * Memory space is mapped 1-1, but I/O space must start from 0.
578 */
579#define CONFIG_PCI /* Enable PCI/PCIE */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400580#define CONFIG_PCIE1 /* PCIE controller 1 */
581#define CONFIG_PCIE2 /* PCIE controller 2 */
582#define CONFIG_PCIE3 /* PCIE controller 3 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800583#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
584#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
585#define CONFIG_PCI_INDIRECT_BRIDGE
586
587#ifdef CONFIG_PCI
588/* controller 1, direct to uli, tgtid 3, Base address 20000 */
589#ifdef CONFIG_PCIE1
590#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
591#ifdef CONFIG_PHYS_64BIT
592#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
593#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
594#else
595#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
596#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
597#endif
598#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
599#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
600#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
601#ifdef CONFIG_PHYS_64BIT
602#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
603#else
604#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
605#endif
606#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
607#endif
608
609/* controller 2, Slot 2, tgtid 2, Base address 201000 */
610#ifdef CONFIG_PCIE2
611#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
612#ifdef CONFIG_PHYS_64BIT
613#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
614#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
615#else
616#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
617#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000
618#endif
619#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
620#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
621#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
622#ifdef CONFIG_PHYS_64BIT
623#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
624#else
625#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
626#endif
627#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
628#endif
629
630/* controller 3, Slot 1, tgtid 1, Base address 202000 */
631#ifdef CONFIG_PCIE3
632#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
633#ifdef CONFIG_PHYS_64BIT
634#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
635#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
636#else
637#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
638#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
639#endif
640#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
641#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
642#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
643#ifdef CONFIG_PHYS_64BIT
644#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
645#else
646#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
647#endif
648#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
649#endif
650
651#define CONFIG_PCI_PNP /* do pci plug-and-play */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800652#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
653#define CONFIG_DOS_PARTITION
654#endif /* CONFIG_PCI */
655
656/*
657 *SATA
658 */
659#define CONFIG_FSL_SATA_V2
660#ifdef CONFIG_FSL_SATA_V2
661#define CONFIG_LIBATA
662#define CONFIG_FSL_SATA
663#define CONFIG_SYS_SATA_MAX_DEVICE 1
664#define CONFIG_SATA1
665#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
666#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
667#define CONFIG_LBA48
668#define CONFIG_CMD_SATA
669#define CONFIG_DOS_PARTITION
Shengzhou Liuaba80042014-11-24 17:11:55 +0800670#endif
671
672/*
673 * USB
674 */
675#define CONFIG_HAS_FSL_DR_USB
676
677#ifdef CONFIG_HAS_FSL_DR_USB
678#define CONFIG_USB_EHCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800679#define CONFIG_USB_STORAGE
680#define CONFIG_USB_EHCI_FSL
681#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liuaba80042014-11-24 17:11:55 +0800682#endif
683
684/*
685 * SDHC
686 */
687#define CONFIG_MMC
688#ifdef CONFIG_MMC
689#define CONFIG_FSL_ESDHC
690#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Shengzhou Liuaba80042014-11-24 17:11:55 +0800691#define CONFIG_GENERIC_MMC
Shengzhou Liuaba80042014-11-24 17:11:55 +0800692#define CONFIG_DOS_PARTITION
693#endif
694
695/* Qman/Bman */
696#ifndef CONFIG_NOBQFMAN
697#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500698#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800699#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
700#ifdef CONFIG_PHYS_64BIT
701#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
702#else
703#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
704#endif
705#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500706#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
707#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
708#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
709#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
710#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
711 CONFIG_SYS_BMAN_CENA_SIZE)
712#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
713#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500714#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Shengzhou Liuaba80042014-11-24 17:11:55 +0800715#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
716#ifdef CONFIG_PHYS_64BIT
717#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
718#else
719#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
720#endif
721#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500722#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
723#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
724#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
725#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
726#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
727 CONFIG_SYS_QMAN_CENA_SIZE)
728#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
729#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liuaba80042014-11-24 17:11:55 +0800730
731#define CONFIG_SYS_DPAA_FMAN
732
733#define CONFIG_QE
734#define CONFIG_U_QE
735/* Default address of microcode for the Linux FMan driver */
736#if defined(CONFIG_SPIFLASH)
737/*
738 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
739 * env, so we got 0x110000.
740 */
741#define CONFIG_SYS_QE_FW_IN_SPIFLASH
742#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
743#define CONFIG_SYS_QE_FW_ADDR 0x130000
744#elif defined(CONFIG_SDCARD)
745/*
746 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
747 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
748 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080(0x820).
749 */
750#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
751#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
752#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
753#elif defined(CONFIG_NAND)
754#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
755#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
756#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
757#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
758/*
759 * Slave has no ucode locally, it can fetch this from remote. When implementing
760 * in two corenet boards, slave's ucode could be stored in master's memory
761 * space, the address can be mapped from slave TLB->slave LAW->
762 * slave SRIO or PCIE outbound window->master inbound window->
763 * master LAW->the ucode address in master's memory space.
764 */
765#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
766#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
767#else
768#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
769#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
770#define CONFIG_SYS_QE_FW_ADDR 0xEFE00000
771#endif
772#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
773#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
774#endif /* CONFIG_NOBQFMAN */
775
776#ifdef CONFIG_SYS_DPAA_FMAN
777#define CONFIG_FMAN_ENET
778#define CONFIG_PHYLIB_10G
779#define CONFIG_PHY_VITESSE
780#define CONFIG_PHY_REALTEK
781#define CONFIG_PHY_TERANETICS
782#define RGMII_PHY1_ADDR 0x1
783#define RGMII_PHY2_ADDR 0x2
784#define SGMII_CARD_AQ_PHY_ADDR_S3 0x3
785#define SGMII_CARD_AQ_PHY_ADDR_S4 0x4
786#define SGMII_CARD_AQ_PHY_ADDR_S5 0x5
787#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
788#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
789#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
790#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
791#endif
792
793#ifdef CONFIG_FMAN_ENET
794#define CONFIG_MII /* MII PHY management */
795#define CONFIG_ETHPRIME "FM1@DTSEC4"
796#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
797#endif
798
799/*
800 * Dynamic MTD Partition support with mtdparts
801 */
802#ifndef CONFIG_SYS_NO_FLASH
803#define CONFIG_MTD_DEVICE
804#define CONFIG_MTD_PARTITIONS
805#define CONFIG_CMD_MTDPARTS
806#define CONFIG_FLASH_CFI_MTD
807#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
808 "spi0=spife110000.0"
809#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
810 "128k(dtb),96m(fs),-(user);"\
811 "fff800000.flash:2m(uboot),9m(kernel),"\
812 "128k(dtb),96m(fs),-(user);spife110000.0:" \
813 "2m(uboot),9m(kernel),128k(dtb),-(user)"
814#endif
815
816/*
817 * Environment
818 */
819#define CONFIG_LOADS_ECHO /* echo on for serial download */
820#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
821
822/*
823 * Command line configuration.
824 */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800825#define CONFIG_CMD_DATE
Shengzhou Liuaba80042014-11-24 17:11:55 +0800826#define CONFIG_CMD_EEPROM
Shengzhou Liuaba80042014-11-24 17:11:55 +0800827#define CONFIG_CMD_ERRATA
Shengzhou Liuaba80042014-11-24 17:11:55 +0800828#define CONFIG_CMD_IRQ
Shengzhou Liuaba80042014-11-24 17:11:55 +0800829#define CONFIG_CMD_REGINFO
Shengzhou Liuaba80042014-11-24 17:11:55 +0800830
831#ifdef CONFIG_PCI
832#define CONFIG_CMD_PCI
Shengzhou Liuaba80042014-11-24 17:11:55 +0800833#endif
834
835/*
836 * Miscellaneous configurable options
837 */
838#define CONFIG_SYS_LONGHELP /* undef to save memory */
839#define CONFIG_CMDLINE_EDITING /* Command-line editing */
840#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
841#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800842#ifdef CONFIG_CMD_KGDB
843#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
844#else
845#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
846#endif
847#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
848#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
849#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
850
851/*
852 * For booting Linux, the board info and command line data
853 * have to be in the first 64 MB of memory, since this is
854 * the maximum mapped by the Linux kernel during initialization.
855 */
856#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
857#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
858
859#ifdef CONFIG_CMD_KGDB
860#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
861#endif
862
863/*
864 * Environment Configuration
865 */
866#define CONFIG_ROOTPATH "/opt/nfsroot"
867#define CONFIG_BOOTFILE "uImage"
868#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
869#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
Shengzhou Liuaba80042014-11-24 17:11:55 +0800870#define CONFIG_BAUDRATE 115200
871#define __USB_PHY_TYPE utmi
872
Shengzhou Liuaba80042014-11-24 17:11:55 +0800873#define CONFIG_EXTRA_ENV_SETTINGS \
874 "hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1;\0" \
875 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
876 "bootargs=root=/dev/ram rw console=ttyS0,115200\0" \
877 "ramdiskfile=t1024qds/ramdisk.uboot\0" \
878 "fdtfile=t1024qds/t1024qds.dtb\0" \
879 "netdev=eth0\0" \
880 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
881 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
882 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
883 "tftpflash=tftpboot $loadaddr $uboot && " \
884 "protect off $ubootaddr +$filesize && " \
885 "erase $ubootaddr +$filesize && " \
886 "cp.b $loadaddr $ubootaddr $filesize && " \
887 "protect on $ubootaddr +$filesize && " \
888 "cmp.b $loadaddr $ubootaddr $filesize\0" \
889 "consoledev=ttyS0\0" \
890 "ramdiskaddr=2000000\0" \
891 "fdtaddr=d00000\0" \
892 "bdev=sda3\0"
893
894#define CONFIG_LINUX \
895 "setenv bootargs root=/dev/ram rw " \
896 "console=$consoledev,$baudrate $othbootargs;" \
897 "setenv ramdiskaddr 0x02000000;" \
898 "setenv fdtaddr 0x00c00000;" \
899 "setenv loadaddr 0x1000000;" \
900 "bootm $loadaddr $ramdiskaddr $fdtaddr"
901
902#define CONFIG_NFSBOOTCOMMAND \
903 "setenv bootargs root=/dev/nfs rw " \
904 "nfsroot=$serverip:$rootpath " \
905 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
906 "console=$consoledev,$baudrate $othbootargs;" \
907 "tftp $loadaddr $bootfile;" \
908 "tftp $fdtaddr $fdtfile;" \
909 "bootm $loadaddr - $fdtaddr"
910
911#define CONFIG_BOOTCOMMAND CONFIG_LINUX
912
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530913/* Hash command with SHA acceleration supported in hardware */
914#ifdef CONFIG_FSL_CAAM
915#define CONFIG_CMD_HASH
916#define CONFIG_SHA_HW_ACCEL
917#endif
918
Shengzhou Liuaba80042014-11-24 17:11:55 +0800919#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530920
Shengzhou Liuaba80042014-11-24 17:11:55 +0800921#endif /* __T1024QDS_H */