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Kumar Gala233fdd52008-08-26 15:01:32 -05001/*
2 * Copyright 2008 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
7 */
8
9#include <common.h>
York Sun5614e712013-09-30 09:22:09 -070010#include <fsl_ddr_sdram.h>
Kumar Gala233fdd52008-08-26 15:01:32 -050011
York Sun5614e712013-09-30 09:22:09 -070012#include <fsl_ddr.h>
Kumar Gala233fdd52008-08-26 15:01:32 -050013/*
14 * Calculate the Density of each Physical Rank.
15 * Returned size is in bytes.
16 *
17 * Study these table from Byte 31 of JEDEC SPD Spec.
18 *
19 * DDR I DDR II
20 * Bit Size Size
21 * --- ----- ------
22 * 7 high 512MB 512MB
23 * 6 256MB 256MB
24 * 5 128MB 128MB
25 * 4 64MB 16GB
26 * 3 32MB 8GB
27 * 2 16MB 4GB
28 * 1 2GB 2GB
29 * 0 low 1GB 1GB
30 *
31 * Reorder Table to be linear by stripping the bottom
32 * 2 or 5 bits off and shifting them up to the top.
33 *
34 */
Kumar Galae7563af2009-06-11 23:42:35 -050035static unsigned long long
Kumar Gala233fdd52008-08-26 15:01:32 -050036compute_ranksize(unsigned int mem_type, unsigned char row_dens)
37{
Kumar Galae7563af2009-06-11 23:42:35 -050038 unsigned long long bsize;
Kumar Gala233fdd52008-08-26 15:01:32 -050039
40 /* Bottom 5 bits up to the top. */
41 bsize = ((row_dens >> 5) | ((row_dens & 31) << 3));
42 bsize <<= 27ULL;
Marek Vasutcd84b1f2011-10-21 14:17:19 +000043 debug("DDR: DDR II rank density = 0x%16llx\n", bsize);
Kumar Gala233fdd52008-08-26 15:01:32 -050044
45 return bsize;
46}
47
48/*
49 * Convert a two-nibble BCD value into a cycle time.
50 * While the spec calls for nano-seconds, picos are returned.
51 *
52 * This implements the tables for bytes 9, 23 and 25 for both
53 * DDR I and II. No allowance for distinguishing the invalid
54 * fields absent for DDR I yet present in DDR II is made.
55 * (That is, cycle times of .25, .33, .66 and .75 ns are
56 * allowed for both DDR II and I.)
57 */
58static unsigned int
59convert_bcd_tenths_to_cycle_time_ps(unsigned int spd_val)
60{
61 /* Table look up the lower nibble, allow DDR I & II. */
62 unsigned int tenths_ps[16] = {
63 0,
64 100,
65 200,
66 300,
67 400,
68 500,
69 600,
70 700,
71 800,
72 900,
73 250, /* This and the next 3 entries valid ... */
74 330, /* ... only for tCK calculations. */
75 660,
76 750,
77 0, /* undefined */
78 0 /* undefined */
79 };
80
81 unsigned int whole_ns = (spd_val & 0xF0) >> 4;
82 unsigned int tenth_ns = spd_val & 0x0F;
83 unsigned int ps = whole_ns * 1000 + tenths_ps[tenth_ns];
84
85 return ps;
86}
87
88static unsigned int
89convert_bcd_hundredths_to_cycle_time_ps(unsigned int spd_val)
90{
91 unsigned int tenth_ns = (spd_val & 0xF0) >> 4;
92 unsigned int hundredth_ns = spd_val & 0x0F;
93 unsigned int ps = tenth_ns * 100 + hundredth_ns * 10;
94
95 return ps;
96}
97
98static unsigned int byte40_table_ps[8] = {
99 0,
100 250,
101 330,
102 500,
103 660,
104 750,
105 0, /* supposed to be RFC, but not sure what that means */
106 0 /* Undefined */
107};
108
109static unsigned int
110compute_trfc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trfc)
111{
112 unsigned int trfc_ps;
113
114 trfc_ps = (((trctrfc_ext & 0x1) * 256) + trfc) * 1000
115 + byte40_table_ps[(trctrfc_ext >> 1) & 0x7];
116
117 return trfc_ps;
118}
119
120static unsigned int
121compute_trc_ps_from_spd(unsigned char trctrfc_ext, unsigned char trc)
122{
123 unsigned int trc_ps;
124
125 trc_ps = trc * 1000 + byte40_table_ps[(trctrfc_ext >> 4) & 0x7];
126
127 return trc_ps;
128}
129
130/*
131 * Determine Refresh Rate. Ignore self refresh bit on DDR I.
132 * Table from SPD Spec, Byte 12, converted to picoseconds and
133 * filled in with "default" normal values.
134 */
135static unsigned int
136determine_refresh_rate_ps(const unsigned int spd_refresh)
137{
138 unsigned int refresh_time_ps[8] = {
139 15625000, /* 0 Normal 1.00x */
140 3900000, /* 1 Reduced .25x */
141 7800000, /* 2 Extended .50x */
142 31300000, /* 3 Extended 2.00x */
143 62500000, /* 4 Extended 4.00x */
144 125000000, /* 5 Extended 8.00x */
145 15625000, /* 6 Normal 1.00x filler */
146 15625000, /* 7 Normal 1.00x filler */
147 };
148
149 return refresh_time_ps[spd_refresh & 0x7];
150}
151
152/*
153 * The purpose of this function is to compute a suitable
154 * CAS latency given the DRAM clock period. The SPD only
155 * defines at most 3 CAS latencies. Typically the slower in
156 * frequency the DIMM runs at, the shorter its CAS latency can.
157 * be. If the DIMM is operating at a sufficiently low frequency,
158 * it may be able to run at a CAS latency shorter than the
159 * shortest SPD-defined CAS latency.
160 *
161 * If a CAS latency is not found, 0 is returned.
162 *
163 * Do this by finding in the standard speed bin table the longest
164 * tCKmin that doesn't exceed the value of mclk_ps (tCK).
165 *
166 * An assumption made is that the SDRAM device allows the
167 * CL to be programmed for a value that is lower than those
168 * advertised by the SPD. This is not always the case,
169 * as those modes not defined in the SPD are optional.
170 *
171 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C
172 * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS,
173 * and tRC for corresponding bin"
174 *
175 * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3
176 * Not certain if any good value exists for CL=2
177 */
York Sunbcb6c2b2010-05-07 09:12:01 -0500178 /* CL2 CL3 CL4 CL5 CL6 CL7*/
179unsigned short ddr2_speed_bins[] = { 0, 5000, 3750, 3000, 2500, 1875 };
Kumar Gala233fdd52008-08-26 15:01:32 -0500180
181unsigned int
182compute_derated_DDR2_CAS_latency(unsigned int mclk_ps)
183{
184 const unsigned int num_speed_bins = ARRAY_SIZE(ddr2_speed_bins);
185 unsigned int lowest_tCKmin_found = 0;
186 unsigned int lowest_tCKmin_CL = 0;
187 unsigned int i;
188
189 debug("mclk_ps = %u\n", mclk_ps);
190
191 for (i = 0; i < num_speed_bins; i++) {
192 unsigned int x = ddr2_speed_bins[i];
193 debug("i=%u, x = %u, lowest_tCKmin_found = %u\n",
194 i, x, lowest_tCKmin_found);
195 if (x && x <= mclk_ps && x >= lowest_tCKmin_found ) {
196 lowest_tCKmin_found = x;
197 lowest_tCKmin_CL = i + 2;
198 }
199 }
200
201 debug("lowest_tCKmin_CL = %u\n", lowest_tCKmin_CL);
202
203 return lowest_tCKmin_CL;
204}
205
206/*
207 * ddr_compute_dimm_parameters for DDR2 SPD
208 *
209 * Compute DIMM parameters based upon the SPD information in spd.
210 * Writes the results to the dimm_params_t structure pointed by pdimm.
211 *
212 * FIXME: use #define for the retvals
213 */
214unsigned int
215ddr_compute_dimm_parameters(const ddr2_spd_eeprom_t *spd,
216 dimm_params_t *pdimm,
217 unsigned int dimm_number)
218{
219 unsigned int retval;
220
221 if (spd->mem_type) {
222 if (spd->mem_type != SPD_MEMTYPE_DDR2) {
223 printf("DIMM %u: is not a DDR2 SPD.\n", dimm_number);
224 return 1;
225 }
226 } else {
227 memset(pdimm, 0, sizeof(dimm_params_t));
228 return 1;
229 }
230
231 retval = ddr2_spd_check(spd);
232 if (retval) {
233 printf("DIMM %u: failed checksum\n", dimm_number);
234 return 2;
235 }
236
237 /*
238 * The part name in ASCII in the SPD EEPROM is not null terminated.
239 * Guarantee null termination here by presetting all bytes to 0
240 * and copying the part name in ASCII from the SPD onto it
241 */
242 memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
243 memcpy(pdimm->mpart, spd->mpart, sizeof(pdimm->mpart) - 1);
244
245 /* DIMM organization parameters */
246 pdimm->n_ranks = (spd->mod_ranks & 0x7) + 1;
247 pdimm->rank_density = compute_ranksize(spd->mem_type, spd->rank_dens);
248 pdimm->capacity = pdimm->n_ranks * pdimm->rank_density;
249 pdimm->data_width = spd->dataw;
250 pdimm->primary_sdram_width = spd->primw;
251 pdimm->ec_sdram_width = spd->ecw;
252
Kyle Moffettc7fd27c2011-03-28 11:35:48 -0400253 /* These are all the types defined by the JEDEC DDR2 SPD 1.3 spec */
Kumar Gala233fdd52008-08-26 15:01:32 -0500254 switch (spd->dimm_type) {
Kyle Moffettc7fd27c2011-03-28 11:35:48 -0400255 case DDR2_SPD_DIMMTYPE_RDIMM:
256 case DDR2_SPD_DIMMTYPE_72B_SO_RDIMM:
257 case DDR2_SPD_DIMMTYPE_MINI_RDIMM:
258 /* Registered/buffered DIMMs */
259 pdimm->registered_dimm = 1;
Kumar Gala233fdd52008-08-26 15:01:32 -0500260 break;
261
Kyle Moffettc7fd27c2011-03-28 11:35:48 -0400262 case DDR2_SPD_DIMMTYPE_UDIMM:
263 case DDR2_SPD_DIMMTYPE_SO_DIMM:
264 case DDR2_SPD_DIMMTYPE_MICRO_DIMM:
265 case DDR2_SPD_DIMMTYPE_MINI_UDIMM:
266 /* Unbuffered DIMMs */
267 pdimm->registered_dimm = 0;
Kumar Gala233fdd52008-08-26 15:01:32 -0500268 break;
269
Kyle Moffettc7fd27c2011-03-28 11:35:48 -0400270 case DDR2_SPD_DIMMTYPE_72B_SO_CDIMM:
Kumar Gala233fdd52008-08-26 15:01:32 -0500271 default:
272 printf("unknown dimm_type 0x%02X\n", spd->dimm_type);
273 return 1;
Kumar Gala233fdd52008-08-26 15:01:32 -0500274 }
275
276 /* SDRAM device parameters */
277 pdimm->n_row_addr = spd->nrow_addr;
278 pdimm->n_col_addr = spd->ncol_addr;
279 pdimm->n_banks_per_sdram_device = spd->nbanks;
280 pdimm->edc_config = spd->config;
281 pdimm->burst_lengths_bitmask = spd->burstl;
282 pdimm->row_density = spd->rank_dens;
283
284 /*
285 * Calculate the Maximum Data Rate based on the Minimum Cycle time.
286 * The SPD clk_cycle field (tCKmin) is measured in tenths of
287 * nanoseconds and represented as BCD.
288 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530289 pdimm->tckmin_x_ps
Kumar Gala233fdd52008-08-26 15:01:32 -0500290 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530291 pdimm->tckmin_x_minus_1_ps
Kumar Gala233fdd52008-08-26 15:01:32 -0500292 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle2);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530293 pdimm->tckmin_x_minus_2_ps
Kumar Gala233fdd52008-08-26 15:01:32 -0500294 = convert_bcd_tenths_to_cycle_time_ps(spd->clk_cycle3);
295
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530296 pdimm->tckmax_ps = convert_bcd_tenths_to_cycle_time_ps(spd->tckmax);
Kumar Gala233fdd52008-08-26 15:01:32 -0500297
298 /*
299 * Compute CAS latencies defined by SPD
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530300 * The SPD caslat_x should have at least 1 and at most 3 bits set.
Kumar Gala233fdd52008-08-26 15:01:32 -0500301 *
302 * If cas_lat after masking is 0, the __ilog2 function returns
303 * 255 into the variable. This behavior is abused once.
304 */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530305 pdimm->caslat_x = __ilog2(spd->cas_lat);
306 pdimm->caslat_x_minus_1 = __ilog2(spd->cas_lat
307 & ~(1 << pdimm->caslat_x));
308 pdimm->caslat_x_minus_2 = __ilog2(spd->cas_lat
309 & ~(1 << pdimm->caslat_x)
310 & ~(1 << pdimm->caslat_x_minus_1));
Kumar Gala233fdd52008-08-26 15:01:32 -0500311
312 /* Compute CAS latencies below that defined by SPD */
313 pdimm->caslat_lowest_derated
314 = compute_derated_DDR2_CAS_latency(get_memory_clk_period_ps());
315
316 /* Compute timing parameters */
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530317 pdimm->trcd_ps = spd->trcd * 250;
318 pdimm->trp_ps = spd->trp * 250;
319 pdimm->tras_ps = spd->tras * 1000;
Kumar Gala233fdd52008-08-26 15:01:32 -0500320
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530321 pdimm->twr_ps = spd->twr * 250;
322 pdimm->twtr_ps = spd->twtr * 250;
323 pdimm->trfc_ps = compute_trfc_ps_from_spd(spd->trctrfc_ext, spd->trfc);
Kumar Gala233fdd52008-08-26 15:01:32 -0500324
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530325 pdimm->trrd_ps = spd->trrd * 250;
326 pdimm->trc_ps = compute_trc_ps_from_spd(spd->trctrfc_ext, spd->trc);
Kumar Gala233fdd52008-08-26 15:01:32 -0500327
328 pdimm->refresh_rate_ps = determine_refresh_rate_ps(spd->refresh);
329
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530330 pdimm->tis_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_setup);
331 pdimm->tih_ps = convert_bcd_hundredths_to_cycle_time_ps(spd->ca_hold);
332 pdimm->tds_ps
Kumar Gala233fdd52008-08-26 15:01:32 -0500333 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_setup);
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530334 pdimm->tdh_ps
Kumar Gala233fdd52008-08-26 15:01:32 -0500335 = convert_bcd_hundredths_to_cycle_time_ps(spd->data_hold);
336
Priyanka Jain0dd38a32013-09-25 10:41:19 +0530337 pdimm->trtp_ps = spd->trtp * 250;
338 pdimm->tdqsq_max_ps = spd->tdqsq * 10;
339 pdimm->tqhs_ps = spd->tqhs * 10;
Kumar Gala233fdd52008-08-26 15:01:32 -0500340
341 return 0;
342}