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stroese5ce08ee2003-09-12 08:41:24 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
stroese5ce08ee2003-09-12 08:41:24 +00006 */
7
8#include <common.h>
9#include <asm/processor.h>
Matthias Fuchsbb57ad42009-02-20 10:19:19 +010010#include <asm/io.h>
stroese5ce08ee2003-09-12 08:41:24 +000011#include <command.h>
12#include <malloc.h>
13
Wolfgang Denkd87080b2006-03-31 18:32:53 +020014DECLARE_GLOBAL_DATA_PTR;
stroese5ce08ee2003-09-12 08:41:24 +000015
wdenkc837dcb2004-01-20 23:12:12 +000016int board_early_init_f (void)
stroese5ce08ee2003-09-12 08:41:24 +000017{
18 /*
19 * IRQ 0-15 405GP internally generated; active high; level sensitive
20 * IRQ 16 405GP internally generated; active low; level sensitive
21 * IRQ 17-24 RESERVED
22 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
23 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
24 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
25 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
26 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
27 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
28 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
29 */
Stefan Roese952e7762009-09-24 09:55:50 +020030 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
31 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
32 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
33 mtdcr(UIC0PR, 0xFFFFFF80); /* set int polarities */
34 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
35 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
36 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
stroese5ce08ee2003-09-12 08:41:24 +000037
38 /*
39 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
40 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020041 mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
stroese5ce08ee2003-09-12 08:41:24 +000042
stroesef2dfe442004-12-16 18:35:58 +000043 /*
44 * Reset CPLD via GPIO13 (CS4) pin
45 */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +010046 out_be32((void *)GPIO0_OR,
47 in_be32((void *)GPIO0_OR) & ~(0x80000000 >> 13));
stroesef2dfe442004-12-16 18:35:58 +000048 udelay(1000); /* wait 1ms */
Matthias Fuchsbb57ad42009-02-20 10:19:19 +010049 out_be32((void *)GPIO0_OR,
50 in_be32((void *)GPIO0_OR) | (0x80000000 >> 13));
stroesef2dfe442004-12-16 18:35:58 +000051 udelay(1000); /* wait 1ms */
52
stroese5ce08ee2003-09-12 08:41:24 +000053 return 0;
54}
55
stroese5ce08ee2003-09-12 08:41:24 +000056int misc_init_r (void)
57{
stroesef2dfe442004-12-16 18:35:58 +000058 /* adjust flash start and offset */
59 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
60 gd->bd->bi_flashoffset = 0;
stroese5ce08ee2003-09-12 08:41:24 +000061
62 return (0);
63}
64
65
66/*
67 * Check Board Identity:
68 */
69
70int checkboard (void)
71{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020072 char str[64];
Wolfgang Denkcdb74972010-07-24 21:55:43 +020073 int i = getenv_f("serial#", str, sizeof(str));
stroese5ce08ee2003-09-12 08:41:24 +000074 unsigned char trans[16] = {0x0,0x8,0x4,0xc,0x2,0xa,0x6,0xe,
wdenk42d1f032003-10-15 23:53:47 +000075 0x1,0x9,0x5,0xd,0x3,0xb,0x7,0xf};
Matthias Fuchs70be6c22009-04-29 09:51:01 +020076 unsigned char id1, id2, rev;
stroese5ce08ee2003-09-12 08:41:24 +000077
78 puts ("Board: ");
79
Matthias Fuchs70be6c22009-04-29 09:51:01 +020080 if (i == -1)
stroese5ce08ee2003-09-12 08:41:24 +000081 puts ("### No HW ID - assuming DP405");
Matthias Fuchs70be6c22009-04-29 09:51:01 +020082 else
stroese5ce08ee2003-09-12 08:41:24 +000083 puts(str);
stroese5ce08ee2003-09-12 08:41:24 +000084
Matthias Fuchsbb57ad42009-02-20 10:19:19 +010085 id1 = trans[(~(in_be32((void *)GPIO0_IR) >> 5)) & 0x0000000f];
86 id2 = trans[(~(in_be32((void *)GPIO0_IR) >> 9)) & 0x0000000f];
Matthias Fuchs70be6c22009-04-29 09:51:01 +020087
Wolfgang Denk8e5e9b92009-07-07 22:35:02 +020088 rev = in_8((void *)0xf0001000);
89 if (rev & 0x10) /* old DP405 compatibility */
90 rev = in_8((void *)0xf0000800);
Matthias Fuchs70be6c22009-04-29 09:51:01 +020091
Wolfgang Denk8e5e9b92009-07-07 22:35:02 +020092 switch (rev & 0xc0) {
93 case 0x00:
94 puts(" (HW=DP405");
95 break;
96 case 0x80:
97 puts(" (HW=DP405/CO");
98 break;
99 case 0xc0:
100 puts(" (HW=DN405");
101 break;
102 }
103 printf(", ID=0x%1X%1X, PLD=0x%02X", id2, id1, rev & 0x0f);
Matthias Fuchs70be6c22009-04-29 09:51:01 +0200104
Wolfgang Denk8e5e9b92009-07-07 22:35:02 +0200105 if ((rev & 0xc0) == 0xc0) {
106 printf(", C5V=%s",
107 in_be32((void *)GPIO0_IR) & 0x40000000 ? "off" : "on");
108 }
109 puts(")\n");
stroese5ce08ee2003-09-12 08:41:24 +0000110
111 return 0;
112}