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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babic8edcde52010-01-20 18:19:10 +01002/*
3 * (C) Copyright 2009
4 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
Stefano Babic8edcde52010-01-20 18:19:10 +01005 */
6
7#ifndef _IMXIMAGE_H_
8#define _IMXIMAGE_H_
9
Fabio Estevam021e79c2014-09-01 09:56:23 -030010#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 */
Peng Fanb55e4f42016-10-11 14:29:09 +080011#define MAX_PLUGIN_CODE_SIZE (64 * 1024)
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000012#define MAX_HW_CFG_SIZE_V1 60 /* Max number of registers imx can set for v1 */
Stefano Babic8edcde52010-01-20 18:19:10 +010013#define APP_CODE_BARKER 0xB1
14#define DCD_BARKER 0xB17219E9
Stefano Babic8edcde52010-01-20 18:19:10 +010015
Bryan O'Donoghue69f06952018-04-24 18:46:31 +010016/* Specify the offset of the IVT in the IMX header as expected by BootROM */
17#define BOOTROM_IVT_HDR_OFFSET 0xC00
18
Marek Vasut6cb83822013-04-25 10:16:02 +000019/*
20 * NOTE: This file must be kept in sync with arch/arm/include/asm/\
Stefano Babic552a8482017-06-29 10:16:06 +020021 * mach-imx/imximage.cfg because tools/imximage.c can not
Marek Vasut6cb83822013-04-25 10:16:02 +000022 * cross-include headers from arch/arm/ and vice-versa.
23 */
Stefano Babic8edcde52010-01-20 18:19:10 +010024#define CMD_DATA_STR "DATA"
Stefano Babic377e3672013-06-26 23:50:06 +020025
26/* Initial Vector Table Offset */
Dirk Behme49d3e272012-02-22 22:50:19 +000027#define FLASH_OFFSET_UNDEFINED 0xFFFFFFFF
Stefano Babic8edcde52010-01-20 18:19:10 +010028#define FLASH_OFFSET_STANDARD 0x400
29#define FLASH_OFFSET_NAND FLASH_OFFSET_STANDARD
30#define FLASH_OFFSET_SD FLASH_OFFSET_STANDARD
31#define FLASH_OFFSET_SPI FLASH_OFFSET_STANDARD
32#define FLASH_OFFSET_ONENAND 0x100
Dirk Behme19b409c2012-01-11 23:28:31 +000033#define FLASH_OFFSET_NOR 0x1000
34#define FLASH_OFFSET_SATA FLASH_OFFSET_STANDARD
Ye.Li9598f8c2015-01-13 15:53:06 +080035#define FLASH_OFFSET_QSPI 0x1000
Peng Fan6609c262018-11-20 10:19:36 +000036#define FLASH_OFFSET_FLEXSPI 0x1000
Stefano Babic8edcde52010-01-20 18:19:10 +010037
Stefano Babic377e3672013-06-26 23:50:06 +020038/* Initial Load Region Size */
39#define FLASH_LOADSIZE_UNDEFINED 0xFFFFFFFF
40#define FLASH_LOADSIZE_STANDARD 0x1000
41#define FLASH_LOADSIZE_NAND FLASH_LOADSIZE_STANDARD
42#define FLASH_LOADSIZE_SD FLASH_LOADSIZE_STANDARD
43#define FLASH_LOADSIZE_SPI FLASH_LOADSIZE_STANDARD
44#define FLASH_LOADSIZE_ONENAND 0x400
45#define FLASH_LOADSIZE_NOR 0x0 /* entire image */
46#define FLASH_LOADSIZE_SATA FLASH_LOADSIZE_STANDARD
Ye.Li9598f8c2015-01-13 15:53:06 +080047#define FLASH_LOADSIZE_QSPI 0x0 /* entire image */
Stefano Babic377e3672013-06-26 23:50:06 +020048
Adrian Alonso0b7f7c32015-07-20 19:04:55 -050049/* Command tags and parameters */
50#define IVT_HEADER_TAG 0xD1
51#define IVT_VERSION 0x40
Peng Fan6609c262018-11-20 10:19:36 +000052#define IVT_VERSION_V3 0x41
Adrian Alonso0b7f7c32015-07-20 19:04:55 -050053#define DCD_HEADER_TAG 0xD2
54#define DCD_VERSION 0x40
55#define DCD_WRITE_DATA_COMMAND_TAG 0xCC
56#define DCD_WRITE_DATA_PARAM 0x4
Peng Fan3e0a71c2017-03-16 14:35:06 +080057#define DCD_WRITE_CLR_BIT_PARAM 0xC
58#define DCD_WRITE_SET_BIT_PARAM 0x1C
Adrian Alonso0b7f7c32015-07-20 19:04:55 -050059#define DCD_CHECK_DATA_COMMAND_TAG 0xCF
60#define DCD_CHECK_BITS_SET_PARAM 0x14
61#define DCD_CHECK_BITS_CLR_PARAM 0x04
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000062
Bryan O'Donoghuef4d8fcc2018-03-26 15:36:45 +010063#ifndef __ASSEMBLY__
Stefano Babic8edcde52010-01-20 18:19:10 +010064enum imximage_cmd {
65 CMD_INVALID,
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000066 CMD_IMAGE_VERSION,
Stefano Babic8edcde52010-01-20 18:19:10 +010067 CMD_BOOT_FROM,
Marek Vasut6cb83822013-04-25 10:16:02 +000068 CMD_BOOT_OFFSET,
Adrian Alonso0b7f7c32015-07-20 19:04:55 -050069 CMD_WRITE_DATA,
70 CMD_WRITE_CLR_BIT,
Peng Fan3e0a71c2017-03-16 14:35:06 +080071 CMD_WRITE_SET_BIT,
Adrian Alonso0b7f7c32015-07-20 19:04:55 -050072 CMD_CHECK_BITS_SET,
73 CMD_CHECK_BITS_CLR,
Stefano Babic0187c982013-06-27 11:42:38 +020074 CMD_CSF,
Peng Fanb55e4f42016-10-11 14:29:09 +080075 CMD_PLUGIN,
Flavio Suligoi7132d382020-01-16 11:32:18 +010076 /* Following on i.MX8MQ/MM */
Peng Fan6609c262018-11-20 10:19:36 +000077 CMD_FIT,
78 CMD_SIGNED_HDMI,
79 CMD_LOADER,
80 CMD_SECOND_LOADER,
81 CMD_DDR_FW,
Peng Fanb8f16832019-09-16 03:09:39 +000082 CMD_ROM_VERSION,
Stefano Babic8edcde52010-01-20 18:19:10 +010083};
84
85enum imximage_fld_types {
86 CFG_INVALID = -1,
87 CFG_COMMAND,
88 CFG_REG_SIZE,
89 CFG_REG_ADDRESS,
90 CFG_REG_VALUE
91};
92
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000093enum imximage_version {
94 IMXIMAGE_VER_INVALID = -1,
95 IMXIMAGE_V1 = 1,
Peng Fan6609c262018-11-20 10:19:36 +000096 IMXIMAGE_V2,
97 IMXIMAGE_V3
Liu Hui-R643438a1edd72011-01-19 09:40:26 +000098};
Stefano Babic8edcde52010-01-20 18:19:10 +010099
100typedef struct {
101 uint32_t type; /* Type of pointer (byte, halfword, word, wait/read) */
102 uint32_t addr; /* Address to write to */
103 uint32_t value; /* Data to write */
104} dcd_type_addr_data_t;
105
106typedef struct {
107 uint32_t barker; /* Barker for sanity check */
108 uint32_t length; /* Device configuration length (without preamble) */
109} dcd_preamble_t;
110
111typedef struct {
112 dcd_preamble_t preamble;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000113 dcd_type_addr_data_t addr_data[MAX_HW_CFG_SIZE_V1];
114} dcd_v1_t;
Stefano Babic8edcde52010-01-20 18:19:10 +0100115
116typedef struct {
117 uint32_t app_code_jump_vector;
118 uint32_t app_code_barker;
119 uint32_t app_code_csf;
120 uint32_t dcd_ptr_ptr;
Stefano Babic5b28e912010-02-05 15:16:02 +0100121 uint32_t super_root_key;
Stefano Babic8edcde52010-01-20 18:19:10 +0100122 uint32_t dcd_ptr;
123 uint32_t app_dest_ptr;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000124} flash_header_v1_t;
Stefano Babic8edcde52010-01-20 18:19:10 +0100125
126typedef struct {
Wolfgang Denk0cf207e2021-09-27 17:42:39 +0200127 uint32_t length; /* Length of data to be read from flash */
Stefano Babic8edcde52010-01-20 18:19:10 +0100128} flash_cfg_parms_t;
129
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000130typedef struct {
131 flash_header_v1_t fhdr;
132 dcd_v1_t dcd_table;
Stefano Babic8edcde52010-01-20 18:19:10 +0100133 flash_cfg_parms_t ext_header;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000134} imx_header_v1_t;
135
136typedef struct {
137 uint32_t addr;
138 uint32_t value;
139} dcd_addr_data_t;
140
141typedef struct {
142 uint8_t tag;
143 uint16_t length;
144 uint8_t version;
145} __attribute__((packed)) ivt_header_t;
146
147typedef struct {
148 uint8_t tag;
149 uint16_t length;
150 uint8_t param;
151} __attribute__((packed)) write_dcd_command_t;
152
Troy Kisky61903b72015-09-14 18:06:31 -0700153struct dcd_v2_cmd {
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000154 write_dcd_command_t write_dcd_command;
155 dcd_addr_data_t addr_data[MAX_HW_CFG_SIZE_V2];
Troy Kisky61903b72015-09-14 18:06:31 -0700156};
157
158typedef struct {
159 ivt_header_t header;
160 struct dcd_v2_cmd dcd_cmd;
Albert ARIBAUD \(3ADEV\)699279c2015-06-19 14:18:30 +0200161 uint32_t padding[1]; /* end up on an 8-byte boundary */
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000162} dcd_v2_t;
163
164typedef struct {
165 uint32_t start;
166 uint32_t size;
167 uint32_t plugin;
168} boot_data_t;
169
170typedef struct {
171 ivt_header_t header;
172 uint32_t entry;
173 uint32_t reserved1;
174 uint32_t dcd_ptr;
175 uint32_t boot_data_ptr;
176 uint32_t self;
177 uint32_t csf;
178 uint32_t reserved2;
179} flash_header_v2_t;
180
181typedef struct {
182 flash_header_v2_t fhdr;
183 boot_data_t boot_data;
Peng Fanb55e4f42016-10-11 14:29:09 +0800184 union {
185 dcd_v2_t dcd_table;
186 char plugin_code[MAX_PLUGIN_CODE_SIZE];
187 } data;
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000188} imx_header_v2_t;
189
Peng Fan6609c262018-11-20 10:19:36 +0000190typedef struct {
191 flash_header_v2_t fhdr;
192 boot_data_t boot_data;
193 uint32_t padding[5];
194} imx_header_v3_t;
195
Marek Vasut895d9962013-04-21 05:52:22 +0000196/* The header must be aligned to 4k on MX53 for NAND boot */
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000197struct imx_header {
198 union {
199 imx_header_v1_t hdr_v1;
200 imx_header_v2_t hdr_v2;
201 } header;
Stefano Babic377e3672013-06-26 23:50:06 +0200202};
Stefano Babic8edcde52010-01-20 18:19:10 +0100203
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000204typedef struct {
205 uint8_t tag[4];
206 uint8_t version[4];
207 uint8_t reserved_1[4];
208 uint8_t read_sample;
209 uint8_t datahold;
210 uint8_t datasetup;
211 uint8_t coladdrwidth;
212 uint8_t devcfgenable;
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500213 uint8_t deviceModeType;
214 uint16_t waitTimeCfgCommands;
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000215 uint8_t devmodeseq[4];
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500216 uint32_t devmodearg;
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000217 uint8_t cmd_enable;
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500218 uint8_t configModeType[3];
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000219 uint8_t cmd_seq[16] ;
220 uint8_t cmd_arg[16];
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500221 uint32_t controllermisc;
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000222 uint8_t dev_type;
223 uint8_t sflash_pad;
224 uint8_t serial_clk;
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500225 uint8_t lut_custom;
226 uint8_t reserved_2[8];
227 uint32_t sflashA1;
228 uint32_t sflashA2;
229 uint32_t sflashB1;
230 uint32_t sflashB2;
231 uint32_t cspadover;
232 uint32_t sclkpadover;
233 uint32_t datapadover;
234 uint32_t dqspadover;
235 uint32_t timeout;
236 uint32_t commandInt;
237 uint16_t datavalid[2];
238 uint16_t busyoffset;
239 uint16_t busybitpolarity;
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000240 uint8_t lut[256];
Jesse Taubeb0adbd62024-01-23 21:15:16 -0500241 uint8_t lutCustomSeq[48];
242 uint8_t reserved_3[16];
243
Mamta Shukla5fe1d4b2022-07-12 14:36:17 +0000244} __attribute__((packed)) fspi_conf;
245
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000246typedef void (*set_dcd_val_t)(struct imx_header *imxhdr,
247 char *name, int lineno,
248 int fld, uint32_t value,
249 uint32_t off);
250
Adrian Alonso0b7f7c32015-07-20 19:04:55 -0500251typedef void (*set_dcd_param_t)(struct imx_header *imxhdr, uint32_t dcd_len,
252 int32_t cmd);
253
Liu Hui-R643438a1edd72011-01-19 09:40:26 +0000254typedef void (*set_dcd_rst_t)(struct imx_header *imxhdr,
255 uint32_t dcd_len,
256 char *name, int lineno);
257
Troy Kiskyad0826d2012-10-03 15:47:08 +0000258typedef void (*set_imx_hdr_t)(struct imx_header *imxhdr, uint32_t dcd_len,
259 uint32_t entry_point, uint32_t flash_offset);
Stefano Babic8edcde52010-01-20 18:19:10 +0100260
Bryan O'Donoghuef4d8fcc2018-03-26 15:36:45 +0100261#endif /* __ASSEMBLY__ */
Stefano Babic8edcde52010-01-20 18:19:10 +0100262#endif /* _IMXIMAGE_H_ */