blob: 7d76af84f03756fd37df39e462a9edf7ba7ca053 [file] [log] [blame]
Troy Kisky0f740cb2013-10-10 15:28:03 -07001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 *
4 * Licensed under the GPL-2 or later.
5 */
Marek Vasutf016f8c2014-02-06 02:43:45 +01006#ifndef __GADGET__CI_UDC_H__
7#define __GADGET__CI_UDC_H__
Troy Kisky0f740cb2013-10-10 15:28:03 -07008
9#define NUM_ENDPOINTS 6
10
Stephen Warrenfcf2ede2014-04-24 17:52:39 -060011#ifdef CONFIG_CI_UDC_HAS_HOSTPC
Marek Vasutf016f8c2014-02-06 02:43:45 +010012struct ci_udc {
Stephen Warrenfcf2ede2014-04-24 17:52:39 -060013 u32 usbcmd; /* 0x130 */
14 u32 usbsts; /* 0x134 */
15 u32 pad1[3];
16 u32 devaddr; /* 0x144 */
17 u32 epinitaddr; /* 0x148 */
18 u32 pad2[10];
19 u32 portsc; /* 0x174 */
20 u32 pad178[(0x1b4 - (0x174 + 4)) / 4];
21 u32 hostpc1_devlc; /* 0x1b4 */
22 u32 pad1b8[(0x1f8 - (0x1b4 + 4)) / 4];
23 u32 usbmode; /* 0x1f8 */
24 u32 pad1fc[(0x208 - (0x1f8 + 4)) / 4];
25 u32 epsetupstat; /* 0x208 */
26 u32 epprime; /* 0x20c */
27 u32 epflush; /* 0x210 */
28 u32 epstat; /* 0x214 */
29 u32 epcomp; /* 0x218 */
30 u32 epctrl[16]; /* 0x21c */
31};
32#else
33struct ci_udc {
Troy Kisky0f740cb2013-10-10 15:28:03 -070034 u32 usbcmd; /* 0x140 */
Troy Kisky0f740cb2013-10-10 15:28:03 -070035 u32 usbsts; /* 0x144 */
36 u32 pad1[3];
37 u32 devaddr; /* 0x154 */
38 u32 epinitaddr; /* 0x158 */
39 u32 pad2[10];
Troy Kisky0f740cb2013-10-10 15:28:03 -070040 u32 portsc; /* 0x184 */
41 u32 pad3[8];
Troy Kisky0f740cb2013-10-10 15:28:03 -070042 u32 usbmode; /* 0x1a8 */
43 u32 epstat; /* 0x1ac */
Troy Kisky0f740cb2013-10-10 15:28:03 -070044 u32 epprime; /* 0x1b0 */
45 u32 epflush; /* 0x1b4 */
46 u32 pad4;
47 u32 epcomp; /* 0x1bc */
Stephen Warrenfcf2ede2014-04-24 17:52:39 -060048 u32 epctrl[16]; /* 0x1c0 */
49};
50
51#define PTS_ENABLE 2
52#define PTS(x) (((x) & 0x3) << 30)
53#define PFSC (1 << 24)
54#endif
55
56#define MICRO_8FRAME 0x8
57#define USBCMD_ITC(x) ((((x) > 0xff) ? 0xff : x) << 16)
58#define USBCMD_FS2 (1 << 15)
59#define USBCMD_RST (1 << 1)
60#define USBCMD_RUN (1)
61
62#define STS_SLI (1 << 8)
63#define STS_URI (1 << 6)
64#define STS_PCI (1 << 2)
65#define STS_UEI (1 << 1)
66#define STS_UI (1 << 0)
67
68#define USBMODE_DEVICE 2
69
70#define EPT_TX(x) (1 << (((x) & 0xffff) + 16))
71#define EPT_RX(x) (1 << ((x) & 0xffff))
72
Troy Kisky0f740cb2013-10-10 15:28:03 -070073#define CTRL_TXE (1 << 23)
74#define CTRL_TXR (1 << 22)
75#define CTRL_RXE (1 << 7)
76#define CTRL_RXR (1 << 6)
77#define CTRL_TXT_BULK (2 << 18)
78#define CTRL_RXT_BULK (2 << 2)
Troy Kisky0f740cb2013-10-10 15:28:03 -070079
Stephen Warren28130062014-05-05 17:48:11 -060080struct ci_req {
81 struct usb_request req;
82 struct list_head queue;
83 /* Bounce buffer allocated if needed to align the transfer */
84 uint8_t *b_buf;
85 uint32_t b_len;
86 /* Buffer for the current transfer. Either req.buf/len or b_buf/len */
87 uint8_t *hw_buf;
88 uint32_t hw_len;
89};
90
Marek Vasutf016f8c2014-02-06 02:43:45 +010091struct ci_ep {
Troy Kisky0f740cb2013-10-10 15:28:03 -070092 struct usb_ep ep;
93 struct list_head queue;
Stephen Warren28130062014-05-05 17:48:11 -060094 bool req_primed;
Troy Kisky0f740cb2013-10-10 15:28:03 -070095 const struct usb_endpoint_descriptor *desc;
Troy Kisky0f740cb2013-10-10 15:28:03 -070096};
97
Marek Vasutf016f8c2014-02-06 02:43:45 +010098struct ci_drv {
Troy Kisky0f740cb2013-10-10 15:28:03 -070099 struct usb_gadget gadget;
Stephen Warrena2d8f922014-05-29 14:53:02 -0600100 struct ci_req *ep0_req;
Troy Kisky0f740cb2013-10-10 15:28:03 -0700101 struct usb_gadget_driver *driver;
102 struct ehci_ctrl *ctrl;
103 struct ept_queue_head *epts;
104 struct ept_queue_item *items[2 * NUM_ENDPOINTS];
105 uint8_t *items_mem;
Marek Vasutf016f8c2014-02-06 02:43:45 +0100106 struct ci_ep ep[NUM_ENDPOINTS];
Troy Kisky0f740cb2013-10-10 15:28:03 -0700107};
108
109struct ept_queue_head {
110 unsigned config;
111 unsigned current; /* read-only */
112
113 unsigned next;
114 unsigned info;
115 unsigned page0;
116 unsigned page1;
117 unsigned page2;
118 unsigned page3;
119 unsigned page4;
120 unsigned reserved_0;
121
122 unsigned char setup_data[8];
123
124 unsigned reserved_1;
125 unsigned reserved_2;
126 unsigned reserved_3;
127 unsigned reserved_4;
128};
129
130#define CONFIG_MAX_PKT(n) ((n) << 16)
131#define CONFIG_ZLT (1 << 29) /* stop on zero-len xfer */
132#define CONFIG_IOS (1 << 15) /* IRQ on setup */
133
134struct ept_queue_item {
135 unsigned next;
136 unsigned info;
137 unsigned page0;
138 unsigned page1;
139 unsigned page2;
140 unsigned page3;
141 unsigned page4;
142 unsigned reserved;
143};
144
145#define TERMINATE 1
146#define INFO_BYTES(n) ((n) << 16)
147#define INFO_IOC (1 << 15)
148#define INFO_ACTIVE (1 << 7)
149#define INFO_HALTED (1 << 6)
150#define INFO_BUFFER_ERROR (1 << 5)
151#define INFO_TX_ERROR (1 << 3)
152#endif