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gerrit.cesnet.cz / github / trini / u-boot / a2ac2b964bfbb20d6791ee94b9034a50cfadb5b0 / . / configs / chromebook_speedy_defconfig
blob: 8d42f0a6809d0a3a606006564058f8388729ac00 [file] [log] [blame]
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]1CONFIG_ARM=y
Tom Rinia2ac2b92021-08-27 21:18:30 -0400[diff] [blame^]2CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]3# CONFIG_SPL_USE_ARCH_MEMCPY is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]4CONFIG_ARCH_ROCKCHIP=y
5CONFIG_SYS_TEXT_BASE=0x00100000
Tom Rini554e5512020-08-10 15:31:07 -0400[diff] [blame]6CONFIG_NR_DRAM_BANKS=1
Tom Rini2bba7802021-06-28 10:17:29 -0400[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-speedy"
Tom Rinic5a6e9f2020-07-06 13:54:25 -0400[diff] [blame]8CONFIG_SPL_TEXT_BASE=0xff704000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]9CONFIG_ROCKCHIP_RK3288=y
10# CONFIG_SPL_MMC_SUPPORT is not set
11CONFIG_TARGET_CHROMEBOOK_SPEEDY=y
Tom Rinid168bcb2019-04-29 15:54:04 -0400[diff] [blame]12CONFIG_SPL_STACK_R_ADDR=0x80000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]13CONFIG_DEBUG_UART_BASE=0xff690000
14CONFIG_DEBUG_UART_CLOCK=24000000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]15CONFIG_SPL_SPI_FLASH_SUPPORT=y
16CONFIG_SPL_SPI_SUPPORT=y
Tom Rini556fd592020-04-28 16:15:47 -0400[diff] [blame]17CONFIG_SPL_PAYLOAD="u-boot.img"
Tom Rinif7d0ae92020-07-28 08:46:52 -0400[diff] [blame]18CONFIG_DEBUG_UART=y
Tom Rini49c8ef02021-08-23 10:25:31 -0400[diff] [blame]19CONFIG_SYS_LOAD_ADDR=0x800800
Simon Glass37304aa2019-07-20 20:51:14 -0600[diff] [blame]20CONFIG_USE_PREBOOT=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]21CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb"
Tom Rini0817daa2020-10-09 12:22:06 -0400[diff] [blame]22CONFIG_SILENT_CONSOLE=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]23# CONFIG_DISPLAY_CPUINFO is not set
24CONFIG_DISPLAY_BOARDINFO_LATE=y
Urja Rannikkofffdf722020-05-13 19:15:21 +0000[diff] [blame]25CONFIG_BOARD_EARLY_INIT_R=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]26# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]27CONFIG_SPL_STACK_R=y
28CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]29# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
Simon Glass1e52db62021-07-14 17:05:32 -0500[diff] [blame]30# CONFIG_SPL_CRC32 is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]31CONFIG_SPL_SPI_LOAD=y
Tom Rini3e5b62f2021-08-10 15:08:46 -0400[diff] [blame]32CONFIG_SYS_SPI_U_BOOT_OFFS=0x20000
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]33CONFIG_CMD_GPIO=y
34CONFIG_CMD_GPT=y
35CONFIG_CMD_I2C=y
36CONFIG_CMD_MMC=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]37CONFIG_CMD_SF_TEST=y
38CONFIG_CMD_SPI=y
39CONFIG_CMD_USB=y
40# CONFIG_CMD_SETEXPR is not set
41CONFIG_CMD_CACHE=y
42CONFIG_CMD_TIME=y
43CONFIG_CMD_PMIC=y
44CONFIG_CMD_REGULATOR=y
45# CONFIG_SPL_DOS_PARTITION is not set
46# CONFIG_SPL_EFI_PARTITION is not set
47CONFIG_SPL_PARTITION_UUIDS=y
48CONFIG_SPL_OF_CONTROL=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]49CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
50CONFIG_SPL_OF_PLATDATA=y
Tom Rini8d8ee472019-11-12 22:46:36 -0500[diff] [blame]51CONFIG_SYS_RELOC_GD_ENV_ADDR=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]52CONFIG_REGMAP=y
53CONFIG_SPL_REGMAP=y
54CONFIG_SYSCON=y
55CONFIG_SPL_SYSCON=y
56# CONFIG_SPL_SIMPLE_BUS is not set
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]57# CONFIG_SPL_BLK is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]58CONFIG_CLK=y
59CONFIG_SPL_CLK=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]60CONFIG_ROCKCHIP_GPIO=y
61CONFIG_I2C_CROS_EC_TUNNEL=y
62CONFIG_SYS_I2C_ROCKCHIP=y
63CONFIG_I2C_MUX=y
64CONFIG_DM_KEYBOARD=y
65CONFIG_CROS_EC_KEYB=y
66CONFIG_CROS_EC=y
67CONFIG_CROS_EC_SPI=y
68CONFIG_PWRSEQ=y
Jaehoon Chung144d0572021-02-16 10:16:56 +0900[diff] [blame]69CONFIG_MMC_PWRSEQ=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]70# CONFIG_SPL_DM_MMC is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]71CONFIG_MMC_DW=y
72CONFIG_MMC_DW_ROCKCHIP=y
Miquel Raynal888f1842019-10-03 19:50:05 +0200[diff] [blame]73CONFIG_MTD=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]74CONFIG_SF_DEFAULT_BUS=2
Patrick Delaunay14453fb2019-02-27 15:20:36 +0100[diff] [blame]75CONFIG_SF_DEFAULT_SPEED=20000000
Urja Rannikko64df5122019-05-13 13:51:03 +0000[diff] [blame]76CONFIG_SPI_FLASH_GIGADEVICE=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]77CONFIG_PINCTRL=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]78CONFIG_PINCONF=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]79CONFIG_SPL_PINCTRL=y
Urja Rannikko5e50f872020-05-13 19:15:23 +0000[diff] [blame]80# CONFIG_SPL_PINCTRL_FULL is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]81CONFIG_DM_PMIC=y
82# CONFIG_SPL_PMIC_CHILDREN is not set
83CONFIG_PMIC_RK8XX=y
84CONFIG_DM_REGULATOR_FIXED=y
85CONFIG_REGULATOR_RK8XX=y
86CONFIG_PWM_ROCKCHIP=y
87CONFIG_RAM=y
88CONFIG_SPL_RAM=y
89CONFIG_DEBUG_UART_SHIFT=2
90CONFIG_ROCKCHIP_SERIAL=y
91CONFIG_ROCKCHIP_SPI=y
92CONFIG_SYSRESET=y
93CONFIG_USB=y
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]94# CONFIG_SPL_DM_USB is not set
95CONFIG_USB_DWC2=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]96CONFIG_ROCKCHIP_USB2_PHY=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]97CONFIG_DM_VIDEO=y
Anatolij Gustschin8a6ffed2020-02-04 22:43:06 +0100[diff] [blame]98# CONFIG_VIDEO_BPP8 is not set
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]99CONFIG_CONSOLE_TRUETYPE=y
100CONFIG_DISPLAY=y
101CONFIG_VIDEO_ROCKCHIP=y
102CONFIG_DISPLAY_ROCKCHIP_EDP=y
103CONFIG_DISPLAY_ROCKCHIP_HDMI=y
104# CONFIG_USE_PRIVATE_LIBGCC is not set
Urja Rannikko7ba79f22019-05-13 13:51:05 +0000[diff] [blame]105CONFIG_SPL_TINY_MEMSET=y
Marty E. Plummer8e2e6012019-01-05 20:12:08 -0600[diff] [blame]106CONFIG_CMD_DHRYSTONE=y
107CONFIG_ERRNO_STR=y