blob: 420cd085f1371c21f6c3bc7bd7f98899f385ffcc [file] [log] [blame]
wdenkcc1c8a12002-11-02 22:58:18 +00001/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC860 1
37#define CONFIG_AMX860 1
38
39#undef CONFIG_8xx_CONS_SMC1 /* Console is on SCC2 */
40#undef CONFIG_8xx_CONS_SMC2
41#define CONFIG_8xx_CONS_SCC2 1
42#undef CONFIG_8xx_CONS_NONE
43#define CONFIG_BAUDRATE 9600
44#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
45
46#define MPC8XX_FACT 10 /* Multiply by 10 */
47#define MPC8XX_XIN 5000000 /* 5 MHz in */
48#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
49
50#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
51
52#if 0
53#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
54#else
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56#endif
57
58#define CONFIG_BOOTCOMMAND \
59 "bootp;" \
60 "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
61 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \
62 "bootm" /* autoboot command */
63
64#undef CONFIG_BOOTARGS
65
66#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
67#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
68#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
69#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
70#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
71#define CONFIG_KGDB_BAUDRATE 9600 /* speed to run kgdb serial port at */
72#endif
73
74
75#undef CONFIG_WATCHDOG /* watchdog disabled */
76
77#define CONFIG_SCC1_ENET 1 /* use SCC1 ethernet */
78
79#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
80
81#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
82 CFG_CMD_DHCP | \
83 CFG_CMD_DATE )
84
85#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
86
87/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
88#include <cmd_confdefs.h>
89
90/*
91 * Miscellaneous configurable options
92 */
93#define CFG_LONGHELP /* undef to save memory */
94#define CFG_PROMPT "=> " /* Monitor Command Prompt */
95#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
96#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
97#else
98#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
99#endif
100#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
101#define CFG_MAXARGS 16 /* max number of command args */
102#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
103
104#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
105#define CFG_MEMTEST_END 0x0200000 /* 1 ... 4 MB in DRAM */
106
107#define CFG_LOAD_ADDR 0x00100000
108
109#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
110
111#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
112
113/*
114 * Low Level Configuration Settings
115 * (address mappings, register initial values, etc.)
116 * You should know what you are doing if you make changes here.
117 */
118
119/*-----------------------------------------------------------------------
120 * Internal Memory Mapped Register
121 */
122#define CFG_IMMR 0xFF000000
123
124/*-----------------------------------------------------------------------
125 * Definitions for initial stack pointer and data area (in DPRAM)
126 */
127#define CFG_INIT_RAM_ADDR CFG_IMMR
128#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
129#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
130#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
131#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
132
133/*-----------------------------------------------------------------------
134 * Start addresses for the final memory configuration
135 * (Set up by the startup code)
136 * Please note that CFG_SDRAM_BASE _must_ start at 0
137 */
138#define CFG_SDRAM_BASE 0x00000000
139#define CFG_FLASH_BASE 0x40000000
140#if defined(DEBUG)
141#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
142#else
143#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
144#endif
145#define CFG_MONITOR_BASE CFG_FLASH_BASE
146#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
147
148/*
149 * U-Boot for AMX board supports two types of memory extension
150 * modules: one that provides 4 MB flash memory, and another one with
151 * 16 MB EDO DRAM.
152 *
153 * The flash module swaps the CS0 and CS1 signals: if the module is
154 * installed, CS0 is connected to Flash on the module and CS1 is
155 * connected to the on-board Flash. This means that you must intall
156 * U-Boot when the Flash module is plugged in, if you plan to use
157 * it.
158 *
159 * To enable support for the DRAM extension card, CONFIG_AMX_RAM_EXT
160 * must be defined. The DRAM module uses CS1.
161 *
162 * Only one of these modules may be installed at a time. If U-Boot
163 * is compiled with the CONFIG_AMX_RAM_EXT option set, it will not
164 * work if the Flash extension module is installed instead of the
165 * DRAM module.
166 */
167#define CONFIG_AMX_RAM_EXT /* 16Mb Ext. DRAM module support */
168
169/*
170 * For booting Linux, the board info and command line data
171 * have to be in the first 8 MB of memory, since this is
172 * the maximum mapped by the Linux kernel during initialization.
173 *
174 * Use 4 MB for without and 8 MB with 16 MB DRAM extension module
175 * (CONFIG_AMX_RAM_EXT)
176 */
177#ifdef CONFIG_AMX_RAM_EXT
178# define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
179#else
180# define CFG_BOOTMAPSZ (4 << 20) /* Initial Memory map for Linux */
181#endif
182/*-----------------------------------------------------------------------
183 * FLASH organization
184 */
185#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
186#define CFG_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
187
188#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
189#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
190
191#define CFG_ENV_IS_IN_FLASH 1
192#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
193#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
194
195/*-----------------------------------------------------------------------
196 * Cache Configuration
197 */
198#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
199#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
200#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
201#endif
202
203/*-----------------------------------------------------------------------
204 * SYPCR - System Protection Control 11-9
205 * SYPCR can only be written once after reset!
206 *-----------------------------------------------------------------------
207 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
208 */
209#if defined(CONFIG_WATCHDOG)
210#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
211 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
212#else
213#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
214#endif
215
216/*-----------------------------------------------------------------------
217 * SIUMCR - SIU Module Configuration 11-6
218 *-----------------------------------------------------------------------
219 * PCMCIA config., multi-function pin tri-state
220 */
221#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
222
223/*-----------------------------------------------------------------------
224 * TBSCR - Time Base Status and Control 11-26
225 *-----------------------------------------------------------------------
226 * Clear Reference Interrupt Status, Timebase freezing enabled
227 */
228#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
229
230/*-----------------------------------------------------------------------
231 * PISCR - Periodic Interrupt Status and Control 11-31
232 *-----------------------------------------------------------------------
233 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
234 */
235#define CFG_PISCR (PISCR_PS | PISCR_PITF)
236
237/*-----------------------------------------------------------------------
238 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
239 *-----------------------------------------------------------------------
240 * set the PLL, the low-power modes and the reset control (15-29)
241 */
242#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
243 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
244
245/*-----------------------------------------------------------------------
246 * SCCR - System Clock and reset Control Register 15-27
247 *-----------------------------------------------------------------------
248 * Set clock output, timebase and RTC source and divider,
249 * power management and some other internal clocks
250 */
251#define SCCR_MASK SCCR_EBDF11
252#define CFG_SCCR (SCCR_TBS|SCCR_COM00|SCCR_DFSYNC00|SCCR_DFBRG00|SCCR_DFNL000|SCCR_DFNH000|SCCR_DFLCD000|SCCR_DFALCD00)
253
254#define CFG_DER 0
255
256/*
257 * Init Memory Controller:
258 *
259 * BR0/1 and OR0/1 (FLASH)
260 */
261
262#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
263#ifndef CONFIG_AMX_RAM_EXT
264#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #1 */
265#endif
266
267#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
268#define CFG_PRELIM_OR_AM 0xFFC00000 /* OR addr mask */
269
270/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
271/* 0x00000800 0x00000400 0x00000100 0x00000030 0x00000004 */
272#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_TRLX)
273
274#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
275
276#define CFG_OR0_PRELIM 0xFFC00954 /* Real values for the board */
277#define CFG_BR0_PRELIM 0x40000001 /* Real values for the board */
278
279#ifndef CONFIG_AMX_RAM_EXT
280#define CFG_OR1_REMAP CFG_OR0_REMAP
281#define CFG_OR1_PRELIM 0xFFC00954 /* Real values for the board */
282#define CFG_BR1_PRELIM 0x60000001 /* Real values for the board */
283#endif
284
285/* DSP ("Glue") Xilinx */
286#define CFG_OR6_PRELIM 0xFFFF8000 /* 32kB, 15 waits, cs after addr, no bursts */
287#define CFG_BR6_PRELIM 0x60000401 /* use GPCM for CS generation, 8 bit port */
288
289/*
290 * Internal Definitions
291 *
292 * Boot Flags
293 */
294#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
295#define BOOTFLAG_WARM 0x02 /* Software reboot */
296
297#endif /* __CONFIG_H */