blob: f1a7853a80e66de881bdd2c6338ce2e27d8672ab [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +02002/*
3 * WORK Microwave work_92105 board configuration file
4 *
5 * (C) Copyright 2014 DENX Software Engineering GmbH
6 * Written-by: Albert ARIBAUD <albert.aribaud@3adev.fr>
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +02007 */
8
9#ifndef __CONFIG_WORK_92105_H__
10#define __CONFIG_WORK_92105_H__
11
12/* SoC and board defines */
13#include <linux/sizes.h>
14#include <asm/arch/cpu.h>
15
16/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020017 * Memory configurations
18 */
Tom Riniaa6e94d2022-11-16 13:10:37 -050019#define CFG_SYS_SDRAM_BASE EMC_DYCS0_BASE
20#define CFG_SYS_SDRAM_SIZE SZ_128M
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020021
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020022/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020023 * U-Boot General Configurations
24 */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020025
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020026/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020027 * NAND chip timings for FIXME: which one?
28 */
29
Tom Rini259ec2c2022-12-04 10:04:38 -050030#define CFG_LPC32XX_NAND_MLC_TCEA_DELAY 333333333
Tom Rinidff9de52022-12-04 10:04:34 -050031#define CFG_LPC32XX_NAND_MLC_BUSY_DELAY 10000000
Tom Riniea932862022-12-04 10:04:35 -050032#define CFG_LPC32XX_NAND_MLC_NAND_TA 18181818
Tom Riniab8c6e32022-12-04 10:04:36 -050033#define CFG_LPC32XX_NAND_MLC_RD_HIGH 31250000
Tom Rini3c35c032022-12-04 10:04:37 -050034#define CFG_LPC32XX_NAND_MLC_RD_LOW 45454545
Tom Rini196690d2022-12-04 10:04:39 -050035#define CFG_LPC32XX_NAND_MLC_WR_HIGH 40000000
Tom Rini39fa1772022-12-04 10:04:40 -050036#define CFG_LPC32XX_NAND_MLC_WR_LOW 83333333
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020037
38/*
39 * NAND
40 */
41
42/* driver configuration */
Tom Rini65cc0e22022-11-16 13:10:41 -050043#define CFG_SYS_MAX_NAND_CHIPS 1
Tom Rini4e590942022-11-12 17:36:51 -050044#define CFG_SYS_NAND_BASE MLC_NAND_BASE
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020045
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020046/*
47 * GPIO
48 */
49
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020050/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020051 * Environment
52 */
53
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020054/*
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020055 * SPL
56 */
57
58/* SPL will be executed at offset 0 */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020059/* SPL will use SRAM as stack */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020060/* Use the framework and generic lib */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020061/* SPL will use serial */
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020062/* SPL will load U-Boot from NAND offset 0x40000 */
Simon Glass98463902022-10-20 18:22:39 -060063/* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_TEXT_BASE */
Tom Rini4e590942022-11-12 17:36:51 -050064#define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE
65#define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE
Albert ARIBAUD \(3ADEV\)412ae532015-03-31 11:40:51 +020066
67/*
68 * Include SoC specific configuration
69 */
70#include <asm/arch/config.h>
71
72#endif /* __CONFIG_WORK_92105_H__*/