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stroesea20b27a2004-12-16 18:05:42 +00001/*
2 * Configuation settings for the esd TASREG board.
3 *
4 * (C) Copyright 2004
5 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef _TASREG_H
31#define _TASREG_H
32
33#ifndef __ASSEMBLY__
34#include <asm/m5249.h>
35#endif
36
37/*
38 * High Level Configuration Options
39 * (easy to change)
40 */
41#define CONFIG_MCF52x2 /* define processor family */
42#define CONFIG_M5249 /* define processor type */
43
44#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
45
46#define CONFIG_BAUDRATE 19200
47#define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
48
49#undef CONFIG_WATCHDOG
50
51#undef CONFIG_MONITOR_IS_IN_RAM /* no pre-loader required!!! ;-) */
52
stroesea20b27a2004-12-16 18:05:42 +000053
Jon Loeligera5562902007-07-08 15:31:57 -050054/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050055 * BOOTP options
56 */
57#define CONFIG_BOOTP_BOOTFILESIZE
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_GATEWAY
60#define CONFIG_BOOTP_HOSTNAME
61
62
63/*
Jon Loeligera5562902007-07-08 15:31:57 -050064 * Command line configuration.
65 */
66#include <config_cmd_default.h>
67
68#define CONFIG_CMD_BSP
69#define CONFIG_CMD_EEPROM
70#define CONFIG_CMD_I2C
71
72#undef CONFIG_CMD_NET
73
74
stroesea20b27a2004-12-16 18:05:42 +000075#define CONFIG_BOOTDELAY 3
76
77#define CFG_PROMPT "=> "
78#define CFG_LONGHELP /* undef to save memory */
79
Jon Loeligera5562902007-07-08 15:31:57 -050080#if defined(CONFIG_CMD_KGDB)
stroesea20b27a2004-12-16 18:05:42 +000081#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
82#else
83#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84#endif
85#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
86#define CFG_MAXARGS 16 /* max number of command args */
87#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
88
89#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
90#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
91#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
92#define CONFIG_LOOPW 1 /* enable loopw command */
93#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
94
95#define CFG_LOAD_ADDR 0x200000 /* default load address */
96
97#define CFG_MEMTEST_START 0x400
98#define CFG_MEMTEST_END 0x380000
99
100#define CFG_HZ 1000
101
102/*
103 * Clock configuration: enable only one of the following options
104 */
105
106#if 0 /* this setting will run the cpu at 11MHz */
107#define CFG_PLL_BYPASS 1 /* bypass PLL for test purpose */
108#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */
109#define CFG_CLK 11289600 /* PLL bypass */
110#endif
111
112#if 0 /* this setting will run the cpu at 70MHz */
113#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
114#undef CFG_FAST_CLK /* MCF5249 can run at 140MHz */
115#define CFG_CLK 72185018 /* The next lower speed */
116#endif
117
118#if 1 /* this setting will run the cpu at 140MHz */
119#undef CFG_PLL_BYPASS /* bypass PLL for test purpose */
120#define CFG_FAST_CLK 1 /* MCF5249 can run at 140MHz */
121#define CFG_CLK 132025600 /* MCF5249 can run at 140MHz */
122#endif
123
124/*
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
128 */
129
130#define CFG_MBAR 0x10000000 /* Register Base Addrs */
131#define CFG_MBAR2 0x80000000
132
133/*-----------------------------------------------------------------------
134 * I2C
135 */
136#define CONFIG_SOFT_I2C
137#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
138#define CFG_I2C_SLAVE 0x7F
139#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC32 */
140#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
141/* mask of address bits that overflow into the "EEPROM chip address" */
142#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
143#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* The Catalyst CAT24WC32 has */
144 /* 32 byte page write mode using*/
145 /* last 5 bits of the address */
146#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
147#define CFG_EEPROM_PAGE_WRITE_ENABLE
148
149#if defined (CONFIG_SOFT_I2C)
150#if 0 /* push-pull */
151#define SDA 0x00800000
152#define SCL 0x00000008
153#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
154#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
155#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
156#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
157#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
158#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
159#define I2C_INIT {OUT1|=SDA;OUT0|=SCL;}
160#define I2C_READ ((IN1&SDA)?1:0)
161#define I2C_SDA(x) {if(x)OUT1|=SDA;else OUT1&=~SDA;}
162#define I2C_SCL(x) {if(x)OUT0|=SCL;else OUT0&=~SCL;}
163#define I2C_DELAY {udelay(5);}
164#define I2C_ACTIVE {DIR1|=SDA;}
165#define I2C_TRISTATE {DIR1&=~SDA;}
166#else /* open-collector */
167#define SDA 0x00800000
168#define SCL 0x00000008
169#define DIR0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_EN))
170#define DIR1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_EN))
171#define OUT0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_OUT))
172#define OUT1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_OUT))
173#define IN0 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO_READ))
174#define IN1 *((volatile ulong*)(CFG_MBAR2+MCFSIM_GPIO1_READ))
175#define I2C_INIT {DIR1&=~SDA;DIR0&=~SCL;OUT1&=~SDA;OUT0&=~SCL;}
176#define I2C_READ ((IN1&SDA)?1:0)
177#define I2C_SDA(x) {if(x)DIR1&=~SDA;else DIR1|=SDA;}
178#define I2C_SCL(x) {if(x)DIR0&=~SCL;else DIR0|=SCL;}
179#define I2C_DELAY {udelay(5);}
180#define I2C_ACTIVE {DIR1|=SDA;}
181#define I2C_TRISTATE {DIR1&=~SDA;}
182#endif
183#endif
184
185/*-----------------------------------------------------------------------
186 * Definitions for initial stack pointer and data area (in DPRAM)
187 */
188#define CFG_INIT_RAM_ADDR 0x20000000
189#define CFG_INIT_RAM_END 0x1000 /* End of used area in internal SRAM */
190#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
191#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
192#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
193
194#define CFG_ENV_IS_IN_FLASH 1
195#define CFG_ENV_ADDR 0xFFC40000 /* Address of Environment Sector*/
196#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
197#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
198
199/*-----------------------------------------------------------------------
200 * Start addresses for the final memory configuration
201 * (Set up by the startup code)
202 * Please note that CFG_SDRAM_BASE _must_ start at 0
203 */
204#define CFG_SDRAM_BASE 0x00000000
205#define CFG_SDRAM_SIZE 16 /* SDRAM size in MB */
206#define CFG_FLASH_BASE 0xffc00000
207
208#if 0 /* test-only */
209#define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
210#endif
211
212#define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400)
213
214#define CFG_MONITOR_LEN 0x20000
215#define CFG_MALLOC_LEN (1 * 1024*1024) /* Reserve 1 MB for malloc() */
216#define CFG_BOOTPARAMS_LEN 64*1024
217
218/*
219 * For booting Linux, the board info and command line data
220 * have to be in the first 8 MB of memory, since this is
221 * the maximum mapped by the Linux kernel during initialization ??
222 */
223#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
224
225/*-----------------------------------------------------------------------
226 * FLASH organization
227 */
228#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
229#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
230
231#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
232#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
233
234#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
235#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
236#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
237/*
238 * The following defines are added for buggy IOP480 byte interface.
239 * All other boards should use the standard values (CPCI405 etc.)
240 */
241#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
242#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
243#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
244
245#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
246
247/*-----------------------------------------------------------------------
248 * Cache Configuration
249 */
250#define CFG_CACHELINE_SIZE 16
251
252/*-----------------------------------------------------------------------
253 * Memory bank definitions
254 */
255
256/* CS0 - AMD Flash, address 0xffc00000 */
257#define CFG_CSAR0 0xffc0
258#define CFG_CSCR0 0x1980 /* WS=0110, AA=1, PS=10 */
259/** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
260#define CFG_CSMR0 0x003f0021 /* 4MB, AA=0, WP=0, C/I=1, V=1 */
261
262/* CS1 - FPGA, address 0xe0000000 */
263#define CFG_CSAR1 0xe000
264#define CFG_CSCR1 0x0d80 /* WS=0011, AA=1, PS=10 */
265#define CFG_CSMR1 0x00010001 /* 128kB, AA=0, WP=0, C/I=0, V=1*/
266
267/*-----------------------------------------------------------------------
268 * Port configuration
269 */
270#define CFG_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
271#define CFG_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54*/
272#define CFG_GPIO_EN 0x00000008 /* Set gpio output enable */
273#define CFG_GPIO1_EN 0x00c70000 /* Set gpio output enable */
274#define CFG_GPIO_OUT 0x00000008 /* Set outputs to default state */
275#define CFG_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
276
277#define CFG_GPIO1_LED 0x00400000 /* user led */
278
279/*-----------------------------------------------------------------------
280 * FPGA stuff
281 */
282#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
283#define CFG_FPGA_MAX_SIZE 512*1024 /* 512kByte is enough for XC2S200*/
284
285/* FPGA program pin configuration */
286#define CFG_FPGA_PRG 0x00010000 /* FPGA program pin (ppc output) */
287#define CFG_FPGA_CLK 0x00040000 /* FPGA clk pin (ppc output) */
288#define CFG_FPGA_DATA 0x00020000 /* FPGA data pin (ppc output) */
289#define CFG_FPGA_INIT 0x00080000 /* FPGA init pin (ppc input) */
290#define CFG_FPGA_DONE 0x00100000 /* FPGA done pin (ppc input) */
291
292#endif /* _TASREG_H */