| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2012 |
| 3 | * Stefano Babic DENX Software Engineering sbabic@denx.de. |
| 4 | * |
| Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 6 | * |
| Anatolij Gustschin | b1e6c4c | 2013-04-30 11:15:33 +0000 | [diff] [blame] | 7 | * Refer doc/README.imximage for more details about how-to configure |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 8 | * and create imximage boot image |
| 9 | * |
| 10 | * The syntax is taken as close as possible with the kwbimage |
| 11 | */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 12 | |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 13 | /* image version */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 14 | IMAGE_VERSION 2 |
| 15 | |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 16 | /* |
| 17 | * Boot Device : one of |
| 18 | * spi, sd (the board has no nand neither onenand) |
| 19 | */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 20 | BOOT_FROM nor |
| 21 | |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 22 | /* |
| 23 | * Device Configuration Data (DCD) |
| 24 | * |
| 25 | * Each entry must have the format: |
| 26 | * Addr-type Address Value |
| 27 | * |
| 28 | * where: |
| 29 | * Addr-type register length (1,2 or 4 bytes) |
| 30 | * Address absolute address of the register |
| 31 | * value value to be stored in the register |
| 32 | */ |
| 33 | /* IOMUX for RAM only */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 34 | DATA 4 0x53fa8554 0x300020 |
| 35 | DATA 4 0x53fa8560 0x300020 |
| 36 | DATA 4 0x53fa8594 0x300020 |
| 37 | DATA 4 0x53fa8584 0x300020 |
| 38 | DATA 4 0x53fa8558 0x300040 |
| 39 | DATA 4 0x53fa8568 0x300040 |
| 40 | DATA 4 0x53fa8590 0x300040 |
| 41 | DATA 4 0x53fa857c 0x300040 |
| 42 | DATA 4 0x53fa8564 0x300040 |
| 43 | DATA 4 0x53fa8580 0x300040 |
| 44 | DATA 4 0x53fa8570 0x300220 |
| 45 | DATA 4 0x53fa8578 0x300220 |
| 46 | DATA 4 0x53fa872c 0x300000 |
| 47 | DATA 4 0x53fa8728 0x300000 |
| 48 | DATA 4 0x53fa871c 0x300000 |
| 49 | DATA 4 0x53fa8718 0x300000 |
| 50 | DATA 4 0x53fa8574 0x300020 |
| 51 | DATA 4 0x53fa8588 0x300020 |
| 52 | DATA 4 0x53fa855c 0x0 |
| 53 | DATA 4 0x53fa858c 0x0 |
| 54 | DATA 4 0x53fa856c 0x300040 |
| 55 | DATA 4 0x53fa86f0 0x300000 |
| 56 | DATA 4 0x53fa8720 0x300000 |
| 57 | DATA 4 0x53fa86fc 0x0 |
| 58 | DATA 4 0x53fa86f4 0x0 |
| 59 | DATA 4 0x53fa8714 0x0 |
| 60 | DATA 4 0x53fa8724 0x4000000 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 61 | |
| 62 | /* DDR RAM */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 63 | DATA 4 0x63fd9088 0x40404040 |
| 64 | DATA 4 0x63fd9090 0x40404040 |
| 65 | DATA 4 0x63fd907C 0x01420143 |
| 66 | DATA 4 0x63fd9080 0x01450146 |
| 67 | DATA 4 0x63fd9018 0x00111740 |
| 68 | DATA 4 0x63fd9000 0x84190000 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 69 | |
| 70 | /* esdcfgX */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 71 | DATA 4 0x63fd900C 0x9f5152e3 |
| 72 | DATA 4 0x63fd9010 0xb68e8a63 |
| 73 | DATA 4 0x63fd9014 0x01ff00db |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 74 | |
| 75 | /* Read/Write command delay */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 76 | DATA 4 0x63fd902c 0x000026d2 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 77 | |
| 78 | /* Out of reset delays */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 79 | DATA 4 0x63fd9030 0x00ff0e21 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 80 | |
| 81 | /* ESDCTL ODT timing control */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 82 | DATA 4 0x63fd9008 0x12273030 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 83 | |
| 84 | /* ESDCTL power down control */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 85 | DATA 4 0x63fd9004 0x0002002d |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 86 | |
| 87 | /* Set registers in DDR memory chips */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 88 | DATA 4 0x63fd901c 0x00008032 |
| 89 | DATA 4 0x63fd901c 0x00008033 |
| 90 | DATA 4 0x63fd901c 0x00028031 |
| 91 | DATA 4 0x63fd901c 0x052080b0 |
| 92 | DATA 4 0x63fd901c 0x04008040 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 93 | |
| 94 | /* ESDCTL refresh control */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 95 | DATA 4 0x63fd9020 0x00005800 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 96 | |
| 97 | /* PHY ZQ HW control */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 98 | DATA 4 0x63fd9040 0x05380003 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 99 | |
| 100 | /* PHY ODT control */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 101 | DATA 4 0x63fd9058 0x00022222 |
| Troy Kisky | 71a988a | 2013-01-18 16:14:24 +0000 | [diff] [blame] | 102 | |
| 103 | /* start DDR3 */ |
| Stefano Babic | 79656d2 | 2012-02-22 00:24:40 +0000 | [diff] [blame] | 104 | DATA 4 0x63fd901c 0x00000000 |