blob: 00fa752996593353216e183a7f6547737817bc97 [file] [log] [blame]
Kumar Galaf852ce72007-11-29 00:15:30 -06001/*
Kumar Galaa09b9b62010-12-30 12:09:53 -06002 * Copyright 2007-2011 Freescale Semiconductor, Inc.
Kumar Galaf852ce72007-11-29 00:15:30 -06003 *
4 * (C) Copyright 2000
5 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <libfdt.h>
28#include <fdt_support.h>
Kumar Gala730b2fc2008-05-29 11:22:06 -050029#include <asm/processor.h>
Vivek Mahajancb0ff652009-09-22 12:48:27 +053030#include <linux/ctype.h>
Kumar Gala6aba33e2009-03-19 03:40:08 -050031#include <asm/io.h>
Kumar Galadb977ab2009-09-10 03:02:13 -050032#include <asm/fsl_portals.h>
Dipen Dudhatda1cd952009-09-02 11:25:08 +053033#ifdef CONFIG_FSL_ESDHC
34#include <fsl_esdhc.h>
35#endif
Kumar Galaf852ce72007-11-29 00:15:30 -060036
Trent Piepho58ec4862008-12-03 15:16:38 -080037DECLARE_GLOBAL_DATA_PTR;
38
Kumar Gala69018ce2008-01-17 08:25:45 -060039extern void ft_qe_setup(void *blob);
Poonam Aggrwalf8027f62009-09-02 19:40:36 +053040extern void ft_fixup_num_cores(void *blob);
Kumar Galaa09b9b62010-12-30 12:09:53 -060041extern void ft_srio_setup(void *blob);
Kim Phillips6b70ffb2008-06-16 15:55:53 -050042
Kumar Galaec2b74f2008-01-17 16:48:33 -060043#ifdef CONFIG_MP
44#include "mp.h"
Kumar Galaec2b74f2008-01-17 16:48:33 -060045
46void ft_fixup_cpu(void *blob, u64 memory_limit)
47{
48 int off;
Peter Tyser5ccd29c2009-10-23 15:55:47 -050049 ulong spin_tbl_addr = get_spin_phys_addr();
Kumar Galac840d262009-03-31 23:11:05 -050050 u32 bootpg = determine_mp_bootpg();
51 u32 id = get_my_id();
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050052 const char *enable_method;
Kumar Galaec2b74f2008-01-17 16:48:33 -060053
54 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
55 while (off != -FDT_ERR_NOTFOUND) {
56 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
57
58 if (reg) {
Matthew McClintockb80d3052010-08-19 13:57:48 -050059 u64 val = *reg * SIZE_BOOT_ENTRY + spin_tbl_addr;
60 val = cpu_to_fdt32(val);
Kumar Galaec2b74f2008-01-17 16:48:33 -060061 if (*reg == id) {
Matthew McClintockb80d3052010-08-19 13:57:48 -050062 fdt_setprop_string(blob, off, "status",
63 "okay");
Kumar Galaec2b74f2008-01-17 16:48:33 -060064 } else {
Kumar Galaec2b74f2008-01-17 16:48:33 -060065 fdt_setprop_string(blob, off, "status",
66 "disabled");
Kumar Galaec2b74f2008-01-17 16:48:33 -060067 }
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050068
69 if (hold_cores_in_reset(0)) {
70#ifdef CONFIG_FSL_CORENET
71 /* Cores held in reset, use BRR to release */
72 enable_method = "fsl,brr-holdoff";
73#else
74 /* Cores held in reset, use EEBPCR to release */
75 enable_method = "fsl,eebpcr-holdoff";
76#endif
77 } else {
78 /* Cores out of reset and in a spin-loop */
79 enable_method = "spin-table";
80
81 fdt_setprop(blob, off, "cpu-release-addr",
82 &val, sizeof(val));
83 }
84
Matthew McClintockb80d3052010-08-19 13:57:48 -050085 fdt_setprop_string(blob, off, "enable-method",
Aaron Sierra9d64c6b2010-09-30 12:22:16 -050086 enable_method);
Kumar Galaec2b74f2008-01-17 16:48:33 -060087 } else {
88 printf ("cpu NULL\n");
89 }
90 off = fdt_node_offset_by_prop_value(blob, off,
91 "device_type", "cpu", 4);
92 }
93
94 /* Reserve the boot page so OSes dont use it */
95 if ((u64)bootpg < memory_limit) {
96 off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
97 if (off < 0)
98 printf("%s: %s\n", __FUNCTION__, fdt_strerror(off));
99 }
100}
101#endif
Kumar Gala69018ce2008-01-17 08:25:45 -0600102
Kumar Gala6aba33e2009-03-19 03:40:08 -0500103#ifdef CONFIG_SYS_FSL_CPC
104static inline void ft_fixup_l3cache(void *blob, int off)
105{
106 u32 line_size, num_ways, size, num_sets;
107 cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
108 u32 cfg0 = in_be32(&cpc->cpccfg0);
109
110 size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
111 num_ways = CPC_CFG0_NUM_WAYS(cfg0);
112 line_size = CPC_CFG0_LINE_SZ(cfg0);
113 num_sets = size / (line_size * num_ways);
114
115 fdt_setprop(blob, off, "cache-unified", NULL, 0);
116 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
117 fdt_setprop_cell(blob, off, "cache-size", size);
118 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
119 fdt_setprop_cell(blob, off, "cache-level", 3);
120#ifdef CONFIG_SYS_CACHE_STASHING
121 fdt_setprop_cell(blob, off, "cache-stash-id", 1);
122#endif
123}
124#else
Kumar Gala1b3e4042009-03-19 09:16:10 -0500125#define ft_fixup_l3cache(x, y)
Kumar Gala6aba33e2009-03-19 03:40:08 -0500126#endif
Kumar Gala1b3e4042009-03-19 09:16:10 -0500127
128#if defined(CONFIG_L2_CACHE)
Kumar Gala730b2fc2008-05-29 11:22:06 -0500129/* return size in kilobytes */
130static inline u32 l2cache_size(void)
131{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132 volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
Kumar Gala730b2fc2008-05-29 11:22:06 -0500133 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
134 u32 ver = SVR_SOC_VER(get_svr());
135
136 switch (l2siz_field) {
137 case 0x0:
138 break;
139 case 0x1:
140 if (ver == SVR_8540 || ver == SVR_8560 ||
141 ver == SVR_8541 || ver == SVR_8541_E ||
142 ver == SVR_8555 || ver == SVR_8555_E)
143 return 128;
144 else
145 return 256;
146 break;
147 case 0x2:
148 if (ver == SVR_8540 || ver == SVR_8560 ||
149 ver == SVR_8541 || ver == SVR_8541_E ||
150 ver == SVR_8555 || ver == SVR_8555_E)
151 return 256;
152 else
153 return 512;
154 break;
155 case 0x3:
156 return 1024;
157 break;
158 }
159
160 return 0;
161}
162
163static inline void ft_fixup_l2cache(void *blob)
164{
165 int len, off;
166 u32 *ph;
167 struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
168 char compat_buf[38];
169
170 const u32 line_size = 32;
171 const u32 num_ways = 8;
172 const u32 size = l2cache_size() * 1024;
173 const u32 num_sets = size / (line_size * num_ways);
174
175 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
176 if (off < 0) {
177 debug("no cpu node fount\n");
178 return;
179 }
180
181 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
182
183 if (ph == NULL) {
184 debug("no next-level-cache property\n");
185 return ;
186 }
187
188 off = fdt_node_offset_by_phandle(blob, *ph);
189 if (off < 0) {
190 printf("%s: %s\n", __func__, fdt_strerror(off));
191 return ;
192 }
193
194 if (cpu) {
Vivek Mahajancb0ff652009-09-22 12:48:27 +0530195 if (isdigit(cpu->name[0]))
196 len = sprintf(compat_buf,
197 "fsl,mpc%s-l2-cache-controller", cpu->name);
198 else
199 len = sprintf(compat_buf,
200 "fsl,%c%s-l2-cache-controller",
201 tolower(cpu->name[0]), cpu->name + 1);
202
Kumar Gala730b2fc2008-05-29 11:22:06 -0500203 sprintf(&compat_buf[len + 1], "cache");
204 }
205 fdt_setprop(blob, off, "cache-unified", NULL, 0);
206 fdt_setprop_cell(blob, off, "cache-block-size", line_size);
Kumar Gala730b2fc2008-05-29 11:22:06 -0500207 fdt_setprop_cell(blob, off, "cache-size", size);
208 fdt_setprop_cell(blob, off, "cache-sets", num_sets);
209 fdt_setprop_cell(blob, off, "cache-level", 2);
210 fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
Kumar Gala1b3e4042009-03-19 09:16:10 -0500211
212 /* we dont bother w/L3 since no platform of this type has one */
213}
214#elif defined(CONFIG_BACKSIDE_L2_CACHE)
215static inline void ft_fixup_l2cache(void *blob)
216{
217 int off, l2_off, l3_off = -1;
218 u32 *ph;
219 u32 l2cfg0 = mfspr(SPRN_L2CFG0);
220 u32 size, line_size, num_ways, num_sets;
221
222 size = (l2cfg0 & 0x3fff) * 64 * 1024;
223 num_ways = ((l2cfg0 >> 14) & 0x1f) + 1;
224 line_size = (((l2cfg0 >> 23) & 0x3) + 1) * 32;
225 num_sets = size / (line_size * num_ways);
226
227 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
228
229 while (off != -FDT_ERR_NOTFOUND) {
230 ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
231
232 if (ph == NULL) {
233 debug("no next-level-cache property\n");
234 goto next;
235 }
236
237 l2_off = fdt_node_offset_by_phandle(blob, *ph);
238 if (l2_off < 0) {
239 printf("%s: %s\n", __func__, fdt_strerror(off));
240 goto next;
241 }
242
Kumar Gala82fd1f82009-03-19 02:53:01 -0500243#ifdef CONFIG_SYS_CACHE_STASHING
244 {
245 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
246 if (reg)
247 fdt_setprop_cell(blob, l2_off, "cache-stash-id",
248 (*reg * 2) + 32 + 1);
249 }
250#endif
251
Kumar Gala1b3e4042009-03-19 09:16:10 -0500252 fdt_setprop(blob, l2_off, "cache-unified", NULL, 0);
253 fdt_setprop_cell(blob, l2_off, "cache-block-size", line_size);
254 fdt_setprop_cell(blob, l2_off, "cache-size", size);
255 fdt_setprop_cell(blob, l2_off, "cache-sets", num_sets);
256 fdt_setprop_cell(blob, l2_off, "cache-level", 2);
257 fdt_setprop(blob, l2_off, "compatible", "cache", 6);
258
259 if (l3_off < 0) {
260 ph = (u32 *)fdt_getprop(blob, l2_off, "next-level-cache", 0);
261
262 if (ph == NULL) {
263 debug("no next-level-cache property\n");
264 goto next;
265 }
266 l3_off = *ph;
267 }
268next:
269 off = fdt_node_offset_by_prop_value(blob, off,
270 "device_type", "cpu", 4);
271 }
272 if (l3_off > 0) {
273 l3_off = fdt_node_offset_by_phandle(blob, l3_off);
274 if (l3_off < 0) {
275 printf("%s: %s\n", __func__, fdt_strerror(off));
276 return ;
277 }
278 ft_fixup_l3cache(blob, l3_off);
279 }
Kumar Gala730b2fc2008-05-29 11:22:06 -0500280}
281#else
282#define ft_fixup_l2cache(x)
283#endif
284
285static inline void ft_fixup_cache(void *blob)
286{
287 int off;
288
289 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
290
291 while (off != -FDT_ERR_NOTFOUND) {
292 u32 l1cfg0 = mfspr(SPRN_L1CFG0);
293 u32 l1cfg1 = mfspr(SPRN_L1CFG1);
294 u32 isize, iline_size, inum_sets, inum_ways;
295 u32 dsize, dline_size, dnum_sets, dnum_ways;
296
297 /* d-side config */
298 dsize = (l1cfg0 & 0x7ff) * 1024;
299 dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
300 dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
301 dnum_sets = dsize / (dline_size * dnum_ways);
302
303 fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
Kumar Gala730b2fc2008-05-29 11:22:06 -0500304 fdt_setprop_cell(blob, off, "d-cache-size", dsize);
305 fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
306
Kumar Gala82fd1f82009-03-19 02:53:01 -0500307#ifdef CONFIG_SYS_CACHE_STASHING
308 {
309 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
310 if (reg)
311 fdt_setprop_cell(blob, off, "cache-stash-id",
312 (*reg * 2) + 32 + 0);
313 }
314#endif
315
Kumar Gala730b2fc2008-05-29 11:22:06 -0500316 /* i-side config */
317 isize = (l1cfg1 & 0x7ff) * 1024;
318 inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
319 iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
320 inum_sets = isize / (iline_size * inum_ways);
321
322 fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
Kumar Gala730b2fc2008-05-29 11:22:06 -0500323 fdt_setprop_cell(blob, off, "i-cache-size", isize);
324 fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
325
326 off = fdt_node_offset_by_prop_value(blob, off,
327 "device_type", "cpu", 4);
328 }
329
330 ft_fixup_l2cache(blob);
331}
332
333
Andy Fleming0e17f022008-10-07 08:09:50 -0500334void fdt_add_enet_stashing(void *fdt)
335{
336 do_fixup_by_compat(fdt, "gianfar", "bd-stash", NULL, 0, 1);
337
338 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-len", 96, 1);
339
340 do_fixup_by_compat_u32(fdt, "gianfar", "rx-stash-idx", 0, 1);
341}
342
Kumar Galabcad21f2009-03-19 02:46:28 -0500343#if defined(CONFIG_SYS_DPAA_FMAN) || defined(CONFIG_SYS_DPAA_PME)
Kumar Gala1b942f72010-07-10 06:38:16 -0500344static void ft_fixup_clks(void *blob, const char *compat, u32 offset,
345 unsigned long freq)
Kumar Galabcad21f2009-03-19 02:46:28 -0500346{
Kumar Gala1b942f72010-07-10 06:38:16 -0500347 phys_addr_t phys = offset + CONFIG_SYS_CCSRBAR_PHYS;
348 int off = fdt_node_offset_by_compat_reg(blob, compat, phys);
Kumar Galabcad21f2009-03-19 02:46:28 -0500349
350 if (off >= 0) {
351 off = fdt_setprop_cell(blob, off, "clock-frequency", freq);
352 if (off > 0)
353 printf("WARNING enable to set clock-frequency "
Kumar Gala1b942f72010-07-10 06:38:16 -0500354 "for %s: %s\n", compat, fdt_strerror(off));
Kumar Galabcad21f2009-03-19 02:46:28 -0500355 }
356}
357
358static void ft_fixup_dpaa_clks(void *blob)
359{
360 sys_info_t sysinfo;
361
362 get_sys_info(&sysinfo);
Kumar Gala1b942f72010-07-10 06:38:16 -0500363 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
364 sysinfo.freqFMan[0]);
Kumar Galabcad21f2009-03-19 02:46:28 -0500365
366#if (CONFIG_SYS_NUM_FMAN == 2)
Kumar Gala1b942f72010-07-10 06:38:16 -0500367 ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
368 sysinfo.freqFMan[1]);
Kumar Galabcad21f2009-03-19 02:46:28 -0500369#endif
370
371#ifdef CONFIG_SYS_DPAA_PME
Kumar Gala1b942f72010-07-10 06:38:16 -0500372 do_fixup_by_compat_u32(blob, "fsl,pme",
373 "clock-frequency", sysinfo.freqPME, 1);
Kumar Galabcad21f2009-03-19 02:46:28 -0500374#endif
375}
376#else
377#define ft_fixup_dpaa_clks(x)
378#endif
379
Liu Yu46df64f2010-01-15 14:58:40 +0800380#ifdef CONFIG_QE
381static void ft_fixup_qe_snum(void *blob)
382{
383 unsigned int svr;
384
385 svr = mfspr(SPRN_SVR);
386 if (SVR_SOC_VER(svr) == SVR_8569_E) {
387 if(IS_SVR_REV(svr, 1, 0))
388 do_fixup_by_compat_u32(blob, "fsl,qe",
389 "fsl,qe-num-snums", 46, 1);
390 else
391 do_fixup_by_compat_u32(blob, "fsl,qe",
392 "fsl,qe-num-snums", 76, 1);
393 }
394}
395#endif
396
Kumar Galaf852ce72007-11-29 00:15:30 -0600397void ft_cpu_setup(void *blob, bd_t *bd)
398{
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500399 int off;
400 int val;
401 sys_info_t sysinfo;
402
Kim Phillips6b70ffb2008-06-16 15:55:53 -0500403 /* delete crypto node if not on an E-processor */
404 if (!IS_E_PROCESSOR(get_svr()))
405 fdt_fixup_crypto_node(blob, 0);
406
Kumar Galaba37aa02008-08-19 15:41:18 -0500407 fdt_fixup_ethernet(blob);
Andy Fleming0e17f022008-10-07 08:09:50 -0500408
409 fdt_add_enet_stashing(blob);
Kumar Galaf852ce72007-11-29 00:15:30 -0600410
411 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
Kumar Gala3c2a67e2009-09-17 01:52:37 -0500412 "timebase-frequency", get_tbclk(), 1);
Kumar Galaf852ce72007-11-29 00:15:30 -0600413 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
414 "bus-frequency", bd->bi_busfreq, 1);
Haiying Wang2fc7eb02009-01-15 11:58:35 -0500415 get_sys_info(&sysinfo);
416 off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
417 while (off != -FDT_ERR_NOTFOUND) {
418 u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0);
419 val = cpu_to_fdt32(sysinfo.freqProcessor[*reg]);
420 fdt_setprop(blob, off, "clock-frequency", &val, 4);
421 off = fdt_node_offset_by_prop_value(blob, off, "device_type",
422 "cpu", 4);
423 }
Kumar Galaf852ce72007-11-29 00:15:30 -0600424 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
425 "bus-frequency", bd->bi_busfreq, 1);
Trent Piepho58ec4862008-12-03 15:16:38 -0800426
427 do_fixup_by_compat_u32(blob, "fsl,pq3-localbus",
428 "bus-frequency", gd->lbc_clk, 1);
429 do_fixup_by_compat_u32(blob, "fsl,elbc",
430 "bus-frequency", gd->lbc_clk, 1);
Kumar Galaf852ce72007-11-29 00:15:30 -0600431#ifdef CONFIG_QE
Kumar Gala69018ce2008-01-17 08:25:45 -0600432 ft_qe_setup(blob);
Liu Yu46df64f2010-01-15 14:58:40 +0800433 ft_fixup_qe_snum(blob);
Kumar Galaf852ce72007-11-29 00:15:30 -0600434#endif
435
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#ifdef CONFIG_SYS_NS16550
Kumar Galaf852ce72007-11-29 00:15:30 -0600437 do_fixup_by_compat_u32(blob, "ns16550",
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438 "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
Kumar Galaf852ce72007-11-29 00:15:30 -0600439#endif
440
441#ifdef CONFIG_CPM2
442 do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
443 "current-speed", bd->bi_baudrate, 1);
444
445 do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
446 "clock-frequency", bd->bi_brgfreq, 1);
447#endif
448
Kumar Gala85f8cda2010-07-10 06:55:41 -0500449#ifdef CONFIG_FSL_CORENET
450 do_fixup_by_compat_u32(blob, "fsl,qoriq-clockgen-1.0",
451 "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
452#endif
453
Kumar Galaf852ce72007-11-29 00:15:30 -0600454 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
Kumar Galaec2b74f2008-01-17 16:48:33 -0600455
456#ifdef CONFIG_MP
457 ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
Poonam Aggrwalf8027f62009-09-02 19:40:36 +0530458 ft_fixup_num_cores(blob);
Kumar Gala8f3a7fa2010-06-09 22:33:53 -0500459#endif
Kumar Gala730b2fc2008-05-29 11:22:06 -0500460
461 ft_fixup_cache(blob);
Dipen Dudhatda1cd952009-09-02 11:25:08 +0530462
463#if defined(CONFIG_FSL_ESDHC)
464 fdt_fixup_esdhc(blob, bd);
465#endif
Kumar Galabcad21f2009-03-19 02:46:28 -0500466
467 ft_fixup_dpaa_clks(blob);
Kumar Galadb977ab2009-09-10 03:02:13 -0500468
469#if defined(CONFIG_SYS_BMAN_MEM_PHYS)
470 fdt_portal(blob, "fsl,bman-portal", "bman-portals",
471 (u64)CONFIG_SYS_BMAN_MEM_PHYS,
472 CONFIG_SYS_BMAN_MEM_SIZE);
473#endif
474
475#if defined(CONFIG_SYS_QMAN_MEM_PHYS)
476 fdt_portal(blob, "fsl,qman-portal", "qman-portals",
477 (u64)CONFIG_SYS_QMAN_MEM_PHYS,
478 CONFIG_SYS_QMAN_MEM_SIZE);
479
480 fdt_fixup_qportals(blob);
481#endif
Kumar Galaa09b9b62010-12-30 12:09:53 -0600482
483#ifdef CONFIG_SYS_SRIO
484 ft_srio_setup(blob);
485#endif
Kumar Galaf852ce72007-11-29 00:15:30 -0600486}