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Donghwa Lee6d4339f2012-04-05 19:36:17 +00001/*
2 * (C) Copyright 2012 Samsung Electronics
3 * Donghwa Lee <dh09.lee@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * aint with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 *
20 */
21
22#ifndef __ASM_ARM_ARCH_FB_H_
23#define __ASM_ARM_ARCH_FB_H_
24
25#ifndef __ASSEMBLY__
Donghwa Leeee93dcf2012-07-26 15:30:49 +000026struct exynos_fb {
Donghwa Lee6d4339f2012-04-05 19:36:17 +000027 unsigned int vidcon0;
28 unsigned int vidcon1;
29 unsigned int vidcon2;
30 unsigned int vidcon3;
31 unsigned int vidtcon0;
32 unsigned int vidtcon1;
33 unsigned int vidtcon2;
34 unsigned int vidtcon3;
35 unsigned int wincon0;
36 unsigned int wincon1;
37 unsigned int wincon2;
38 unsigned int wincon3;
39 unsigned int wincon4;
40
41 unsigned int winshmap;
42 unsigned int res1;
43
44 unsigned int winchmap2;
45 unsigned int vidosd0a;
46 unsigned int vidosd0b;
47 unsigned int vidosd0c;
48 unsigned int res2;
49
50 unsigned int vidosd1a;
51 unsigned int vidosd1b;
52 unsigned int vidosd1c;
53 unsigned int vidosd1d;
54
55 unsigned int vidosd2a;
56 unsigned int vidosd2b;
57 unsigned int vidosd2c;
58 unsigned int vidosd2d;
59
60 unsigned int vidosd3a;
61 unsigned int vidosd3b;
62 unsigned int vidosd3c;
63 unsigned int res3;
64
65 unsigned int vidosd4a;
66 unsigned int vidosd4b;
67 unsigned int vidosd4c;
68 unsigned int res4[5];
69
70 unsigned int vidw00add0b0;
71 unsigned int vidw00add0b1;
72 unsigned int vidw01add0b0;
73 unsigned int vidw01add0b1;
74
75 unsigned int vidw02add0b0;
76 unsigned int vidw02add0b1;
77 unsigned int vidw03add0b0;
78 unsigned int vidw03add0b1;
79 unsigned int vidw04add0b0;
80 unsigned int vidw04add0b1;
81 unsigned int res5[2];
82
83 unsigned int vidw00add1b0;
84 unsigned int vidw00add1b1;
85 unsigned int vidw01add1b0;
86 unsigned int vidw01add1b1;
87
88 unsigned int vidw02add1b0;
89 unsigned int vidw02add1b1;
90 unsigned int vidw03add1b0;
91 unsigned int vidw03add1b1;
92
93 unsigned int vidw04add1b0;
94 unsigned int vidw04add1b1;
95 unsigned int res7[2];
96
97 unsigned int vidw00add2;
98 unsigned int vidw01add2;
99 unsigned int vidw02add2;
100 unsigned int vidw03add2;
101 unsigned int vidw04add2;
102 unsigned int res8[7];
103
104 unsigned int vidintcon0;
105 unsigned int vidintcon1;
106 unsigned int res9[1];
107
108 unsigned int w1keycon0;
109 unsigned int w1keycon1;
110 unsigned int w2keycon0;
111 unsigned int w2keycon1;
112 unsigned int w3keycon0;
113 unsigned int w3keycon1;
114 unsigned int w4keycon0;
115 unsigned int w4keycon1;
116
117 unsigned int w1keyalpha;
118 unsigned int w2keyalpha;
119 unsigned int w3keyalpha;
120 unsigned int w4keyalpha;
121
122 unsigned int dithmode;
123 unsigned int res10[2];
124
125 unsigned int win0map;
126 unsigned int win1map;
127 unsigned int win2map;
128 unsigned int win3map;
129 unsigned int win4map;
130 unsigned int res11[1];
131
132 unsigned int wpalcon_h;
133 unsigned int wpalcon_l;
134
135 unsigned int trigcon;
136 unsigned int res12[2];
137
138 unsigned int i80ifcona0;
139 unsigned int i80ifcona1;
140 unsigned int i80ifconb0;
141 unsigned int i80ifconb1;
142
143 unsigned int colorgaincon;
144 unsigned int res13[2];
145
146 unsigned int ldi_cmdcon0;
147 unsigned int ldi_cmdcon1;
148 unsigned int res14[1];
149
150 /* To be updated */
151
152 unsigned char res15[156];
153 unsigned int dualrgb;
Donghwa Leea29c8322012-07-02 01:16:08 +0000154 unsigned char res16[16];
155 unsigned int dp_mie_clkcon;
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000156};
157#endif
158
Donghwa Leeee93dcf2012-07-26 15:30:49 +0000159/* LCD IF register offset */
160#define EXYNOS4_LCD_IF_BASE_OFFSET 0x0
161#define EXYNOS5_LCD_IF_BASE_OFFSET 0x20000
162
163static inline unsigned int exynos_fimd_get_base_offset(void)
164{
165 if (cpu_is_exynos5())
166 return EXYNOS5_LCD_IF_BASE_OFFSET;
167 else
168 return EXYNOS4_LCD_IF_BASE_OFFSET;
169}
170
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000171/*
172 * Register offsets
173*/
174#define EXYNOS_WINCON(x) (x * 0x04)
175#define EXYNOS_VIDOSD(x) (x * 0x10)
176#define EXYNOS_BUFFER_OFFSET(x) (x * 0x08)
177#define EXYNOS_BUFFER_SIZE(x) (x * 0x04)
178
179/*
180 * Bit Definitions
181*/
182
183/* VIDCON0 */
184#define EXYNOS_VIDCON0_DSI_DISABLE (0 << 30)
185#define EXYNOS_VIDCON0_DSI_ENABLE (1 << 30)
186#define EXYNOS_VIDCON0_SCAN_PROGRESSIVE (0 << 29)
187#define EXYNOS_VIDCON0_SCAN_INTERLACE (1 << 29)
188#define EXYNOS_VIDCON0_SCAN_MASK (1 << 29)
189#define EXYNOS_VIDCON0_VIDOUT_RGB (0 << 26)
190#define EXYNOS_VIDCON0_VIDOUT_ITU (1 << 26)
191#define EXYNOS_VIDCON0_VIDOUT_I80LDI0 (2 << 26)
192#define EXYNOS_VIDCON0_VIDOUT_I80LDI1 (3 << 26)
193#define EXYNOS_VIDCON0_VIDOUT_WB_RGB (4 << 26)
194#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI0 (6 << 26)
195#define EXYNOS_VIDCON0_VIDOUT_WB_I80LDI1 (7 << 26)
196#define EXYNOS_VIDCON0_VIDOUT_MASK (7 << 26)
197#define EXYNOS_VIDCON0_PNRMODE_RGB_P (0 << 17)
198#define EXYNOS_VIDCON0_PNRMODE_BGR_P (1 << 17)
199#define EXYNOS_VIDCON0_PNRMODE_RGB_S (2 << 17)
200#define EXYNOS_VIDCON0_PNRMODE_BGR_S (3 << 17)
201#define EXYNOS_VIDCON0_PNRMODE_MASK (3 << 17)
202#define EXYNOS_VIDCON0_PNRMODE_SHIFT (17)
203#define EXYNOS_VIDCON0_CLKVALUP_ALWAYS (0 << 16)
204#define EXYNOS_VIDCON0_CLKVALUP_START_FRAME (1 << 16)
205#define EXYNOS_VIDCON0_CLKVALUP_MASK (1 << 16)
206#define EXYNOS_VIDCON0_CLKVAL_F(x) (((x) & 0xff) << 6)
207#define EXYNOS_VIDCON0_VCLKEN_NORMAL (0 << 5)
208#define EXYNOS_VIDCON0_VCLKEN_FREERUN (1 << 5)
209#define EXYNOS_VIDCON0_VCLKEN_MASK (1 << 5)
210#define EXYNOS_VIDCON0_CLKDIR_DIRECTED (0 << 4)
211#define EXYNOS_VIDCON0_CLKDIR_DIVIDED (1 << 4)
212#define EXYNOS_VIDCON0_CLKDIR_MASK (1 << 4)
213#define EXYNOS_VIDCON0_CLKSEL_HCLK (0 << 2)
214#define EXYNOS_VIDCON0_CLKSEL_SCLK (1 << 2)
215#define EXYNOS_VIDCON0_CLKSEL_MASK (1 << 2)
216#define EXYNOS_VIDCON0_ENVID_ENABLE (1 << 1)
217#define EXYNOS_VIDCON0_ENVID_DISABLE (0 << 1)
218#define EXYNOS_VIDCON0_ENVID_F_ENABLE (1 << 0)
219#define EXYNOS_VIDCON0_ENVID_F_DISABLE (0 << 0)
220
221/* VIDCON1 */
222#define EXYNOS_VIDCON1_IVCLK_FALLING_EDGE (0 << 7)
223#define EXYNOS_VIDCON1_IVCLK_RISING_EDGE (1 << 7)
224#define EXYNOS_VIDCON1_IHSYNC_NORMAL (0 << 6)
225#define EXYNOS_VIDCON1_IHSYNC_INVERT (1 << 6)
226#define EXYNOS_VIDCON1_IVSYNC_NORMAL (0 << 5)
227#define EXYNOS_VIDCON1_IVSYNC_INVERT (1 << 5)
228#define EXYNOS_VIDCON1_IVDEN_NORMAL (0 << 4)
229#define EXYNOS_VIDCON1_IVDEN_INVERT (1 << 4)
230
231/* VIDCON2 */
232#define EXYNOS_VIDCON2_EN601_DISABLE (0 << 23)
233#define EXYNOS_VIDCON2_EN601_ENABLE (1 << 23)
234#define EXYNOS_VIDCON2_EN601_MASK (1 << 23)
235#define EXYNOS_VIDCON2_WB_DISABLE (0 << 15)
236#define EXYNOS_VIDCON2_WB_ENABLE (1 << 15)
237#define EXYNOS_VIDCON2_WB_MASK (1 << 15)
238#define EXYNOS_VIDCON2_TVFORMATSEL_HW (0 << 14)
239#define EXYNOS_VIDCON2_TVFORMATSEL_SW (1 << 14)
240#define EXYNOS_VIDCON2_TVFORMATSEL_MASK (1 << 14)
241#define EXYNOS_VIDCON2_TVFORMATSEL_YUV422 (1 << 12)
242#define EXYNOS_VIDCON2_TVFORMATSEL_YUV444 (2 << 12)
243#define EXYNOS_VIDCON2_TVFORMATSEL_YUV_MASK (3 << 12)
244#define EXYNOS_VIDCON2_ORGYUV_YCBCR (0 << 8)
245#define EXYNOS_VIDCON2_ORGYUV_CBCRY (1 << 8)
246#define EXYNOS_VIDCON2_ORGYUV_MASK (1 << 8)
247#define EXYNOS_VIDCON2_YUVORD_CBCR (0 << 7)
248#define EXYNOS_VIDCON2_YUVORD_CRCB (1 << 7)
249#define EXYNOS_VIDCON2_YUVORD_MASK (1 << 7)
250
251/* PRTCON */
252#define EXYNOS_PRTCON_UPDATABLE (0 << 11)
253#define EXYNOS_PRTCON_PROTECT (1 << 11)
254
255/* VIDTCON0 */
256#define EXYNOS_VIDTCON0_VBPDE(x) (((x) & 0xff) << 24)
257#define EXYNOS_VIDTCON0_VBPD(x) (((x) & 0xff) << 16)
258#define EXYNOS_VIDTCON0_VFPD(x) (((x) & 0xff) << 8)
259#define EXYNOS_VIDTCON0_VSPW(x) (((x) & 0xff) << 0)
260
261/* VIDTCON1 */
262#define EXYNOS_VIDTCON1_VFPDE(x) (((x) & 0xff) << 24)
263#define EXYNOS_VIDTCON1_HBPD(x) (((x) & 0xff) << 16)
264#define EXYNOS_VIDTCON1_HFPD(x) (((x) & 0xff) << 8)
265#define EXYNOS_VIDTCON1_HSPW(x) (((x) & 0xff) << 0)
266
267/* VIDTCON2 */
268#define EXYNOS_VIDTCON2_LINEVAL(x) (((x) & 0x7ff) << 11)
269#define EXYNOS_VIDTCON2_HOZVAL(x) (((x) & 0x7ff) << 0)
Donghwa Leeee93dcf2012-07-26 15:30:49 +0000270#define EXYNOS_VIDTCON2_LINEVAL_E(x) ((((x) & 0x800) >> 11) << 23)
271#define EXYNOS_VIDTCON2_HOZVAL_E(x) ((((x) & 0x800) >> 11) << 22)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000272
273/* Window 0~4 Control - WINCONx */
274#define EXYNOS_WINCON_DATAPATH_DMA (0 << 22)
275#define EXYNOS_WINCON_DATAPATH_LOCAL (1 << 22)
276#define EXYNOS_WINCON_DATAPATH_MASK (1 << 22)
277#define EXYNOS_WINCON_BUFSEL_0 (0 << 20)
278#define EXYNOS_WINCON_BUFSEL_1 (1 << 20)
279#define EXYNOS_WINCON_BUFSEL_MASK (1 << 20)
280#define EXYNOS_WINCON_BUFSEL_SHIFT (20)
281#define EXYNOS_WINCON_BUFAUTO_DISABLE (0 << 19)
282#define EXYNOS_WINCON_BUFAUTO_ENABLE (1 << 19)
283#define EXYNOS_WINCON_BUFAUTO_MASK (1 << 19)
284#define EXYNOS_WINCON_BITSWP_DISABLE (0 << 18)
285#define EXYNOS_WINCON_BITSWP_ENABLE (1 << 18)
286#define EXYNOS_WINCON_BITSWP_SHIFT (18)
287#define EXYNOS_WINCON_BYTESWP_DISABLE (0 << 17)
288#define EXYNOS_WINCON_BYTESWP_ENABLE (1 << 17)
289#define EXYNOS_WINCON_BYTESWP_SHIFT (17)
290#define EXYNOS_WINCON_HAWSWP_DISABLE (0 << 16)
291#define EXYNOS_WINCON_HAWSWP_ENABLE (1 << 16)
292#define EXYNOS_WINCON_HAWSWP_SHIFT (16)
293#define EXYNOS_WINCON_WSWP_DISABLE (0 << 15)
294#define EXYNOS_WINCON_WSWP_ENABLE (1 << 15)
295#define EXYNOS_WINCON_WSWP_SHIFT (15)
296#define EXYNOS_WINCON_INRGB_RGB (0 << 13)
297#define EXYNOS_WINCON_INRGB_YUV (1 << 13)
298#define EXYNOS_WINCON_INRGB_MASK (1 << 13)
299#define EXYNOS_WINCON_BURSTLEN_16WORD (0 << 9)
300#define EXYNOS_WINCON_BURSTLEN_8WORD (1 << 9)
301#define EXYNOS_WINCON_BURSTLEN_4WORD (2 << 9)
302#define EXYNOS_WINCON_BURSTLEN_MASK (3 << 9)
303#define EXYNOS_WINCON_ALPHA_MULTI_DISABLE (0 << 7)
304#define EXYNOS_WINCON_ALPHA_MULTI_ENABLE (1 << 7)
305#define EXYNOS_WINCON_BLD_PLANE (0 << 6)
306#define EXYNOS_WINCON_BLD_PIXEL (1 << 6)
307#define EXYNOS_WINCON_BLD_MASK (1 << 6)
308#define EXYNOS_WINCON_BPPMODE_1BPP (0 << 2)
309#define EXYNOS_WINCON_BPPMODE_2BPP (1 << 2)
310#define EXYNOS_WINCON_BPPMODE_4BPP (2 << 2)
311#define EXYNOS_WINCON_BPPMODE_8BPP_PAL (3 << 2)
312#define EXYNOS_WINCON_BPPMODE_8BPP (4 << 2)
313#define EXYNOS_WINCON_BPPMODE_16BPP_565 (5 << 2)
314#define EXYNOS_WINCON_BPPMODE_16BPP_A555 (6 << 2)
315#define EXYNOS_WINCON_BPPMODE_18BPP_666 (8 << 2)
316#define EXYNOS_WINCON_BPPMODE_18BPP_A665 (9 << 2)
317#define EXYNOS_WINCON_BPPMODE_24BPP_888 (0xb << 2)
318#define EXYNOS_WINCON_BPPMODE_24BPP_A887 (0xc << 2)
319#define EXYNOS_WINCON_BPPMODE_32BPP (0xd << 2)
320#define EXYNOS_WINCON_BPPMODE_16BPP_A444 (0xe << 2)
321#define EXYNOS_WINCON_BPPMODE_15BPP_555 (0xf << 2)
322#define EXYNOS_WINCON_BPPMODE_MASK (0xf << 2)
323#define EXYNOS_WINCON_BPPMODE_SHIFT (2)
324#define EXYNOS_WINCON_ALPHA0_SEL (0 << 1)
325#define EXYNOS_WINCON_ALPHA1_SEL (1 << 1)
326#define EXYNOS_WINCON_ALPHA_SEL_MASK (1 << 1)
327#define EXYNOS_WINCON_ENWIN_DISABLE (0 << 0)
328#define EXYNOS_WINCON_ENWIN_ENABLE (1 << 0)
329
330/* WINCON1 special */
331#define EXYNOS_WINCON1_VP_DISABLE (0 << 24)
332#define EXYNOS_WINCON1_VP_ENABLE (1 << 24)
333#define EXYNOS_WINCON1_LOCALSEL_FIMC1 (0 << 23)
334#define EXYNOS_WINCON1_LOCALSEL_VP (1 << 23)
335#define EXYNOS_WINCON1_LOCALSEL_MASK (1 << 23)
336
337/* WINSHMAP */
338#define EXYNOS_WINSHMAP_PROTECT(x) (((x) & 0x1f) << 10)
339#define EXYNOS_WINSHMAP_CH_ENABLE(x) (1 << (x))
340#define EXYNOS_WINSHMAP_CH_DISABLE(x) (1 << (x))
341#define EXYNOS_WINSHMAP_LOCAL_ENABLE(x) (0x20 << (x))
342#define EXYNOS_WINSHMAP_LOCAL_DISABLE(x) (0x20 << (x))
343
344/* VIDOSDxA, VIDOSDxB */
345#define EXYNOS_VIDOSD_LEFT_X(x) (((x) & 0x7ff) << 11)
346#define EXYNOS_VIDOSD_TOP_Y(x) (((x) & 0x7ff) << 0)
347#define EXYNOS_VIDOSD_RIGHT_X(x) (((x) & 0x7ff) << 11)
348#define EXYNOS_VIDOSD_BOTTOM_Y(x) (((x) & 0x7ff) << 0)
Donghwa Leeee93dcf2012-07-26 15:30:49 +0000349#define EXYNOS_VIDOSD_RIGHT_X_E(x) (((x) & 0x1) << 23)
350#define EXYNOS_VIDOSD_BOTTOM_Y_E(x) (((x) & 0x1) << 22)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000351
352/* VIDOSD0C, VIDOSDxD */
353#define EXYNOS_VIDOSD_SIZE(x) (((x) & 0xffffff) << 0)
354
355/* VIDOSDxC (1~4) */
356#define EXYNOS_VIDOSD_ALPHA0_R(x) (((x) & 0xf) << 20)
357#define EXYNOS_VIDOSD_ALPHA0_G(x) (((x) & 0xf) << 16)
358#define EXYNOS_VIDOSD_ALPHA0_B(x) (((x) & 0xf) << 12)
359#define EXYNOS_VIDOSD_ALPHA1_R(x) (((x) & 0xf) << 8)
360#define EXYNOS_VIDOSD_ALPHA1_G(x) (((x) & 0xf) << 4)
361#define EXYNOS_VIDOSD_ALPHA1_B(x) (((x) & 0xf) << 0)
362#define EXYNOS_VIDOSD_ALPHA0_SHIFT (12)
363#define EXYNOS_VIDOSD_ALPHA1_SHIFT (0)
364
365/* Start Address */
366#define EXYNOS_VIDADDR_START_VBANK(x) (((x) & 0xff) << 24)
367#define EXYNOS_VIDADDR_START_VBASEU(x) (((x) & 0xffffff) << 0)
368
369/* End Address */
370#define EXYNOS_VIDADDR_END_VBASEL(x) (((x) & 0xffffff) << 0)
371
372/* Buffer Size */
373#define EXYNOS_VIDADDR_OFFSIZE(x) (((x) & 0x1fff) << 13)
374#define EXYNOS_VIDADDR_PAGEWIDTH(x) (((x) & 0x1fff) << 0)
Donghwa Leeee93dcf2012-07-26 15:30:49 +0000375#define EXYNOS_VIDADDR_OFFSIZE_E(x) ((((x) & 0x2000) >> 13) << 27)
376#define EXYNOS_VIDADDR_PAGEWIDTH_E(x) ((((x) & 0x2000) >> 13) << 26)
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000377
378/* WIN Color Map */
379#define EXYNOS_WINMAP_COLOR(x) ((x) & 0xffffff)
380
381/* VIDINTCON0 */
382#define EXYNOS_VIDINTCON0_SYSMAINCON_DISABLE (0 << 19)
383#define EXYNOS_VIDINTCON0_SYSMAINCON_ENABLE (1 << 19)
384#define EXYNOS_VIDINTCON0_SYSSUBCON_DISABLE (0 << 18)
385#define EXYNOS_VIDINTCON0_SYSSUBCON_ENABLE (1 << 18)
386#define EXYNOS_VIDINTCON0_SYSIFDONE_DISABLE (0 << 17)
387#define EXYNOS_VIDINTCON0_SYSIFDONE_ENABLE (1 << 17)
388#define EXYNOS_VIDINTCON0_FRAMESEL0_BACK (0 << 15)
389#define EXYNOS_VIDINTCON0_FRAMESEL0_VSYNC (1 << 15)
390#define EXYNOS_VIDINTCON0_FRAMESEL0_ACTIVE (2 << 15)
391#define EXYNOS_VIDINTCON0_FRAMESEL0_FRONT (3 << 15)
392#define EXYNOS_VIDINTCON0_FRAMESEL0_MASK (3 << 15)
393#define EXYNOS_VIDINTCON0_FRAMESEL1_NONE (0 << 13)
394#define EXYNOS_VIDINTCON0_FRAMESEL1_BACK (1 << 13)
395#define EXYNOS_VIDINTCON0_FRAMESEL1_VSYNC (2 << 13)
396#define EXYNOS_VIDINTCON0_FRAMESEL1_FRONT (3 << 13)
397#define EXYNOS_VIDINTCON0_INTFRMEN_DISABLE (0 << 12)
398#define EXYNOS_VIDINTCON0_INTFRMEN_ENABLE (1 << 12)
399#define EXYNOS_VIDINTCON0_FIFOSEL_WIN4 (1 << 11)
400#define EXYNOS_VIDINTCON0_FIFOSEL_WIN3 (1 << 10)
401#define EXYNOS_VIDINTCON0_FIFOSEL_WIN2 (1 << 9)
402#define EXYNOS_VIDINTCON0_FIFOSEL_WIN1 (1 << 6)
403#define EXYNOS_VIDINTCON0_FIFOSEL_WIN0 (1 << 5)
404#define EXYNOS_VIDINTCON0_FIFOSEL_ALL (0x73 << 5)
405#define EXYNOS_VIDINTCON0_FIFOSEL_MASK (0x73 << 5)
406#define EXYNOS_VIDINTCON0_FIFOLEVEL_25 (0 << 2)
407#define EXYNOS_VIDINTCON0_FIFOLEVEL_50 (1 << 2)
408#define EXYNOS_VIDINTCON0_FIFOLEVEL_75 (2 << 2)
409#define EXYNOS_VIDINTCON0_FIFOLEVEL_EMPTY (3 << 2)
410#define EXYNOS_VIDINTCON0_FIFOLEVEL_FULL (4 << 2)
411#define EXYNOS_VIDINTCON0_FIFOLEVEL_MASK (7 << 2)
412#define EXYNOS_VIDINTCON0_INTFIFO_DISABLE (0 << 1)
413#define EXYNOS_VIDINTCON0_INTFIFO_ENABLE (1 << 1)
414#define EXYNOS_VIDINTCON0_INT_DISABLE (0 << 0)
415#define EXYNOS_VIDINTCON0_INT_ENABLE (1 << 0)
416#define EXYNOS_VIDINTCON0_INT_MASK (1 << 0)
417
418/* VIDINTCON1 */
419#define EXYNOS_VIDINTCON1_INTVPPEND (1 << 5)
420#define EXYNOS_VIDINTCON1_INTI80PEND (1 << 2)
421#define EXYNOS_VIDINTCON1_INTFRMPEND (1 << 1)
422#define EXYNOS_VIDINTCON1_INTFIFOPEND (1 << 0)
423
424/* WINMAP */
425#define EXYNOS_WINMAP_ENABLE (1 << 24)
426
427/* WxKEYCON0 (1~4) */
428#define EXYNOS_KEYCON0_KEYBLEN_DISABLE (0 << 26)
429#define EXYNOS_KEYCON0_KEYBLEN_ENABLE (1 << 26)
430#define EXYNOS_KEYCON0_KEY_DISABLE (0 << 25)
431#define EXYNOS_KEYCON0_KEY_ENABLE (1 << 25)
432#define EXYNOS_KEYCON0_DIRCON_MATCH_FG (0 << 24)
433#define EXYNOS_KEYCON0_DIRCON_MATCH_BG (1 << 24)
434#define EXYNOS_KEYCON0_COMPKEY(x) (((x) & 0xffffff) << 0)
435
436/* WxKEYCON1 (1~4) */
437#define EXYNOS_KEYCON1_COLVAL(x) (((x) & 0xffffff) << 0)
438
439/* DUALRGB */
440#define EXYNOS_DUALRGB_BYPASS_SINGLE (0x00 << 0)
441#define EXYNOS_DUALRGB_BYPASS_DUAL (0x01 << 0)
442#define EXYNOS_DUALRGB_MIE_DUAL (0x10 << 0)
443#define EXYNOS_DUALRGB_MIE_SINGLE (0x11 << 0)
444#define EXYNOS_DUALRGB_LINESPLIT (0x0 << 2)
445#define EXYNOS_DUALRGB_FRAMESPLIT (0x1 << 2)
446#define EXYNOS_DUALRGB_SUB_CNT(x) ((x & 0xfff) << 4)
447#define EXYNOS_DUALRGB_VDEN_EN_DISABLE (0x0 << 16)
448#define EXYNOS_DUALRGB_VDEN_EN_ENABLE (0x1 << 16)
449#define EXYNOS_DUALRGB_MAIN_CNT(x) ((x & 0xfff) << 18)
450
451/* I80IFCONA0 and I80IFCONA1 */
452#define EXYNOS_LCD_CS_SETUP(x) (((x) & 0xf) << 16)
453#define EXYNOS_LCD_WR_SETUP(x) (((x) & 0xf) << 12)
454#define EXYNOS_LCD_WR_ACT(x) (((x) & 0xf) << 8)
455#define EXYNOS_LCD_WR_HOLD(x) (((x) & 0xf) << 4)
456#define EXYNOS_RSPOL_LOW (0 << 2)
457#define EXYNOS_RSPOL_HIGH (1 << 2)
458#define EXYNOS_I80IFEN_DISABLE (0 << 0)
459#define EXYNOS_I80IFEN_ENABLE (1 << 0)
460
461/* TRIGCON */
462#define EXYNOS_I80SOFT_TRIG_EN (1 << 0)
463#define EXYNOS_I80START_TRIG (1 << 1)
464#define EXYNOS_I80STATUS_TRIG_DONE (1 << 2)
465
Donghwa Leeee93dcf2012-07-26 15:30:49 +0000466/* DP_MIE_CLKCON */
467#define EXYNOS_DP_MIE_DISABLE (0 << 0)
468#define EXYNOS_DP_CLK_ENABLE (1 << 1)
469#define EXYNOS_MIE_CLK_ENABLE (3 << 0)
470
Donghwa Lee6d4339f2012-04-05 19:36:17 +0000471#endif /* _REGS_FB_H */