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wdenk0e6d7982004-03-14 00:07:33 +00001/*
2 * Copyright (C) 2004 PaulReynolds@lhsolutions.com
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23
24#include <common.h>
25#include "ocotea.h"
26#include <asm/processor.h>
27#include <spd_sdram.h>
28#include <440gx_enet.h>
29
30#define BOOT_SMALL_FLASH 32 /* 00100000 */
31#define FLASH_ONBD_N 2 /* 00000010 */
32#define FLASH_SRAM_SEL 1 /* 00000001 */
33
34long int fixed_sdram (void);
35void fpga_init (void);
36
37int board_early_init_f (void)
38{
wdenk4b248f32004-03-14 16:51:43 +000039 unsigned long mfr;
wdenk0e6d7982004-03-14 00:07:33 +000040 /*-------------------------------------------------------------------------+
41 | Initialize EBC CONFIG
42 +-------------------------------------------------------------------------*/
43 mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
44 EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
45 EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
46 EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
47 EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
48
49 /*-------------------------------------------------------------------------+
50 | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
51 +-------------------------------------------------------------------------*/
52 mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(8)|
53 EBC_BXAP_BCE_DISABLE|
54 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
55 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
56 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
57 EBC_BXAP_BEM_WRITEONLY|
58 EBC_BXAP_PEN_DISABLED);
59 mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(0xFFE00000)|
60 EBC_BXCR_BS_2MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
61
62 /*-------------------------------------------------------------------------+
63 | 8KB NVRAM/RTC. Initialize bank 1 with default values.
64 +-------------------------------------------------------------------------*/
65 mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
66 EBC_BXAP_BCE_DISABLE|
67 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
68 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
69 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
70 EBC_BXAP_BEM_WRITEONLY|
71 EBC_BXAP_PEN_DISABLED);
72 mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|
73 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
74
75 /*-------------------------------------------------------------------------+
76 | 4 MB FLASH. Initialize bank 2 with default values.
77 +-------------------------------------------------------------------------*/
78 mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
79 EBC_BXAP_BCE_DISABLE|
80 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
81 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
82 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
83 EBC_BXAP_BEM_WRITEONLY|
84 EBC_BXAP_PEN_DISABLED);
85 mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0xFF800000)|
86 EBC_BXCR_BS_4MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
87
88 /*-------------------------------------------------------------------------+
89 | FPGA. Initialize bank 7 with default values.
90 +-------------------------------------------------------------------------*/
91 mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
92 EBC_BXAP_BCE_DISABLE|
93 EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
94 EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
95 EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
96 EBC_BXAP_BEM_WRITEONLY|
97 EBC_BXAP_PEN_DISABLED);
98 mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|
99 EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
100
101 /*--------------------------------------------------------------------
102 * Setup the interrupt controller polarities, triggers, etc.
103 *-------------------------------------------------------------------*/
104 mtdcr (uic0sr, 0xffffffff); /* clear all */
105 mtdcr (uic0er, 0x00000000); /* disable all */
106 mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
107 mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */
108 mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */
109 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
110 mtdcr (uic0sr, 0xffffffff); /* clear all */
111
112 mtdcr (uic1sr, 0xffffffff); /* clear all */
113 mtdcr (uic1er, 0x00000000); /* disable all */
114 mtdcr (uic1cr, 0x00000000); /* all non-critical */
115 mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
116 mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
117 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
118 mtdcr (uic1sr, 0xffffffff); /* clear all */
119
wdenk4b248f32004-03-14 16:51:43 +0000120 mtdcr (uic2sr, 0xffffffff); /* clear all */
121 mtdcr (uic2er, 0x00000000); /* disable all */
122 mtdcr (uic2cr, 0x00000000); /* all non-critical */
123 mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
124 mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
125 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
126 mtdcr (uic2sr, 0xffffffff); /* clear all */
127
128 mtdcr (uicb0sr, 0xfc000000); /* clear all */
129 mtdcr (uicb0er, 0x00000000); /* disable all */
130 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
131 mtdcr (uicb0pr, 0xfc000000); /* */
132 mtdcr (uicb0tr, 0x00000000); /* */
133 mtdcr (uicb0vr, 0x00000001); /* */
134 mfsdr (sdr_mfr, mfr);
135 mfr &= ~SDR0_MFR_ECS_MASK;
136/* mtsdr(sdr_mfr, mfr); */
wdenk0e6d7982004-03-14 00:07:33 +0000137 fpga_init();
138
139 return 0;
140}
141
142
143int checkboard (void)
144{
145 sys_info_t sysinfo;
146
147 get_sys_info (&sysinfo);
148
149 printf ("Board: IBM 440GX Evaluation Board\n");
150 printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
151 printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
152 printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
153 printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
154 printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
155 return (0);
156}
157
158
159long int initdram (int board_type)
160{
161 long dram_size = 0;
162
163#if defined(CONFIG_SPD_EEPROM)
164 dram_size = spd_sdram (0);
165#else
166 dram_size = fixed_sdram ();
167#endif
168 return dram_size;
169}
170
171
172#if defined(CFG_DRAM_TEST)
173int testdram (void)
174{
175 uint *pstart = (uint *) 0x00000000;
176 uint *pend = (uint *) 0x08000000;
177 uint *p;
178
179 for (p = pstart; p < pend; p++)
180 *p = 0xaaaaaaaa;
181
182 for (p = pstart; p < pend; p++) {
183 if (*p != 0xaaaaaaaa) {
184 printf ("SDRAM test fails at: %08x\n", (uint) p);
185 return 1;
186 }
187 }
188
189 for (p = pstart; p < pend; p++)
190 *p = 0x55555555;
191
192 for (p = pstart; p < pend; p++) {
193 if (*p != 0x55555555) {
194 printf ("SDRAM test fails at: %08x\n", (uint) p);
195 return 1;
196 }
197 }
198 return 0;
199}
200#endif
201
202#if !defined(CONFIG_SPD_EEPROM)
203/*************************************************************************
204 * fixed sdram init -- doesn't use serial presence detect.
205 *
206 * Assumes: 128 MB, non-ECC, non-registered
207 * PLB @ 133 MHz
208 *
209 ************************************************************************/
210long int fixed_sdram (void)
211{
212 uint reg;
213
214 /*--------------------------------------------------------------------
215 * Setup some default
216 *------------------------------------------------------------------*/
217 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
218 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
219 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
220 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
221 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
222
223 /*--------------------------------------------------------------------
224 * Setup for board-specific specific mem
225 *------------------------------------------------------------------*/
226 /*
227 * Following for CAS Latency = 2.5 @ 133 MHz PLB
228 */
229 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
230 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
231 /* RA=10 RD=3 */
232 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
233 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
234 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
235 udelay (400); /* Delay 200 usecs (min) */
236
237 /*--------------------------------------------------------------------
238 * Enable the controller, then wait for DCEN to complete
239 *------------------------------------------------------------------*/
240 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
241 for (;;) {
242 mfsdram (mem_mcsts, reg);
243 if (reg & 0x80000000)
244 break;
245 }
246
247 return (128 * 1024 * 1024); /* 128 MB */
248}
249#endif /* !defined(CONFIG_SPD_EEPROM) */
250
251
252/*************************************************************************
253 * pci_pre_init
254 *
255 * This routine is called just prior to registering the hose and gives
256 * the board the opportunity to check things. Returning a value of zero
257 * indicates that things are bad & PCI initialization should be aborted.
258 *
259 * Different boards may wish to customize the pci controller structure
260 * (add regions, override default access routines, etc) or perform
261 * certain pre-initialization actions.
262 *
263 ************************************************************************/
264#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
265int pci_pre_init(struct pci_controller * hose )
266{
267 unsigned long strap;
268
269 /*--------------------------------------------------------------------------+
270 * The ocotea board is always configured as the host & requires the
271 * PCI arbiter to be enabled.
272 *--------------------------------------------------------------------------*/
273 mfsdr(sdr_sdstp1, strap);
274 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
275 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
276 return 0;
277 }
278
279 return 1;
280}
281#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
282
283/*************************************************************************
284 * pci_target_init
285 *
286 * The bootstrap configuration provides default settings for the pci
287 * inbound map (PIM). But the bootstrap config choices are limited and
288 * may not be sufficient for a given board.
289 *
290 ************************************************************************/
291#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
292void pci_target_init(struct pci_controller * hose )
293{
294 DECLARE_GLOBAL_DATA_PTR;
295
296 /*--------------------------------------------------------------------------+
297 * Disable everything
298 *--------------------------------------------------------------------------*/
299 out32r( PCIX0_PIM0SA, 0 ); /* disable */
300 out32r( PCIX0_PIM1SA, 0 ); /* disable */
301 out32r( PCIX0_PIM2SA, 0 ); /* disable */
302 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
303
304 /*--------------------------------------------------------------------------+
305 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
306 * options to not support sizes such as 128/256 MB.
307 *--------------------------------------------------------------------------*/
308 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
309 out32r( PCIX0_PIM0LAH, 0 );
310 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
311
312 out32r( PCIX0_BAR0, 0 );
313
314 /*--------------------------------------------------------------------------+
315 * Program the board's subsystem id/vendor id
316 *--------------------------------------------------------------------------*/
317 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
318 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
319
320 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
321}
322#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
323
324
325/*************************************************************************
326 * is_pci_host
327 *
328 * This routine is called to determine if a pci scan should be
329 * performed. With various hardware environments (especially cPCI and
330 * PPMC) it's insufficient to depend on the state of the arbiter enable
331 * bit in the strap register, or generic host/adapter assumptions.
332 *
333 * Rather than hard-code a bad assumption in the general 440 code, the
334 * 440 pci code requires the board to decide at runtime.
335 *
336 * Return 0 for adapter mode, non-zero for host (monarch) mode.
337 *
338 *
339 ************************************************************************/
340#if defined(CONFIG_PCI)
341int is_pci_host(struct pci_controller *hose)
342{
343 /* The ocotea board is always configured as host. */
344 return(1);
345}
346#endif /* defined(CONFIG_PCI) */
347
348
349void fpga_init(void)
350{
351 unsigned long group;
352 unsigned long sdr0_pfc0;
353 unsigned long sdr0_pfc1;
354 unsigned long sdr0_cust0;
355 unsigned long pvr;
356
357 mfsdr (sdr_pfc0, sdr0_pfc0);
358 mfsdr (sdr_pfc1, sdr0_pfc1);
359 group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
360 pvr = get_pvr ();
361
362 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
363 if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
364 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
365 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
366 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
367 FPGA_REG2_EXT_INTFACE_ENABLE);
368 mtsdr (sdr_pfc0, sdr0_pfc0);
369 mtsdr (sdr_pfc1, sdr0_pfc1);
370 } else {
371 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
372 switch (group)
373 {
374 case 0:
375 case 1:
376 case 2:
377 /* CPU trace A */
378 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
379 FPGA_REG2_EXT_INTFACE_ENABLE);
380 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
381 mtsdr (sdr_pfc0, sdr0_pfc0);
382 mtsdr (sdr_pfc1, sdr0_pfc1);
383 break;
384 case 3:
385 case 4:
386 case 5:
387 case 6:
388 /* CPU trace B - Over EBMI */
389 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
390 mtsdr (sdr_pfc0, sdr0_pfc0);
391 mtsdr (sdr_pfc1, sdr0_pfc1);
392 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
393 FPGA_REG2_EXT_INTFACE_DISABLE);
394 break;
395 }
396 }
397
398 /* Initialize the ethernet specific functions in the fpga */
399 mfsdr(sdr_pfc1, sdr0_pfc1);
400 mfsdr(sdr_cust0, sdr0_cust0);
401 if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
402 ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
403 (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
404 {
405 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
406 {
407 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
408 FPGA_REG3_ENET_GROUP7);
409 }
410 else
411 {
412 if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
413 {
414 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
415 FPGA_REG3_ENET_GROUP7);
416 }
417 else
418 {
419 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
420 FPGA_REG3_ENET_GROUP8);
421 }
422 }
423 }
424 else
425 {
426 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
427 {
428 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
429 FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
430 }
431 else
432 {
433 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
434 FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
435 }
436 }
437 out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
438 FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
439 FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
440
441 /* reset the gigabyte phy if necessary */
442 if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
443 {
444 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
445 {
446 out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
447 udelay(10000);
448 out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
449 }
450 else
451 {
452 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
453 udelay(10000);
454 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
455 }
456 }
457
458 /* Turn off the LED's */
459 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
460 FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
461 FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
462
463 return;
464}
465
466#ifdef CONFIG_POST
467/*
468 * Returns 1 if keys pressed to start the power-on long-running tests
469 * Called from board_init_f().
470 */
471int post_hotkeys_pressed(void)
472{
473
474 return (ctrlc());
475}
476#endif