Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2012 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 8 | #ifndef _TEGRA_COMMON_H_ |
| 9 | #define _TEGRA_COMMON_H_ |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 10 | #include <linux/sizes.h> |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 11 | #include <linux/stringify.h> |
| 12 | |
| 13 | /* |
| 14 | * High Level Configuration Options |
| 15 | */ |
| 16 | #define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 17 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
| 18 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 19 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
| 20 | |
Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 21 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
| 22 | #ifndef CONFIG_ARM64 |
Rob Herring | 31df989 | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 23 | #define CONFIG_SYS_TIMER_RATE 1000000 |
| 24 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE |
Thierry Reding | f41f0a1 | 2015-07-28 11:35:54 +0200 | [diff] [blame] | 25 | #endif |
Rob Herring | 31df989 | 2013-10-04 10:22:47 -0500 | [diff] [blame] | 26 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 27 | /* |
| 28 | * Display CPU and Board information |
| 29 | */ |
| 30 | #define CONFIG_DISPLAY_CPUINFO |
| 31 | #define CONFIG_DISPLAY_BOARDINFO |
| 32 | |
| 33 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 34 | |
| 35 | /* Environment */ |
| 36 | #define CONFIG_ENV_VARS_UBOOT_CONFIG |
| 37 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */ |
| 38 | |
| 39 | /* |
| 40 | * Size of malloc() pool |
| 41 | */ |
Przemyslaw Marczak | 52a7c98 | 2015-03-04 14:01:30 +0100 | [diff] [blame] | 42 | #ifdef CONFIG_DFU_MMC |
| 43 | #define CONFIG_SYS_MALLOC_LEN ((4 << 20) + \ |
| 44 | CONFIG_SYS_DFU_DATA_BUF_SIZE) |
| 45 | #else |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 46 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */ |
Przemyslaw Marczak | 52a7c98 | 2015-03-04 14:01:30 +0100 | [diff] [blame] | 47 | #endif |
Thierry Reding | d1e5b40 | 2014-12-09 22:25:23 -0700 | [diff] [blame] | 48 | |
Thierry Reding | 6527268 | 2015-07-27 11:45:26 -0600 | [diff] [blame] | 49 | #ifndef CONFIG_ARM64 |
Thierry Reding | d1e5b40 | 2014-12-09 22:25:23 -0700 | [diff] [blame] | 50 | #define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ |
Thierry Reding | 6527268 | 2015-07-27 11:45:26 -0600 | [diff] [blame] | 51 | #endif |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 52 | |
| 53 | /* |
Tom Warren | bfcf46d | 2013-02-26 12:18:48 +0000 | [diff] [blame] | 54 | * NS16550 Configuration |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 55 | */ |
Simon Glass | 858530a | 2014-09-04 16:27:36 -0600 | [diff] [blame] | 56 | #define CONFIG_TEGRA_SERIAL |
Simon Glass | 858530a | 2014-09-04 16:27:36 -0600 | [diff] [blame] | 57 | #define CONFIG_SYS_NS16550 |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 58 | |
| 59 | /* |
Stephen Warren | f175603 | 2014-04-18 10:56:11 -0600 | [diff] [blame] | 60 | * Common HW configuration. |
| 61 | * If this varies between SoCs later, move to tegraNN-common.h |
| 62 | * Note: This is number of devices, not max device ID. |
| 63 | */ |
| 64 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
| 65 | |
| 66 | /* |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 67 | * select serial console configuration |
| 68 | */ |
| 69 | #define CONFIG_CONS_INDEX 1 |
| 70 | |
| 71 | /* allow to overwrite serial and ethaddr */ |
| 72 | #define CONFIG_ENV_OVERWRITE |
| 73 | #define CONFIG_BAUDRATE 115200 |
| 74 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 75 | /* turn on command-line edit/hist/auto */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 76 | #define CONFIG_COMMAND_HISTORY |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 77 | |
Stephen Warren | 11d9c03 | 2013-02-28 15:03:48 +0000 | [diff] [blame] | 78 | /* turn on commonly used storage-related commands */ |
Stephen Warren | 11d9c03 | 2013-02-28 15:03:48 +0000 | [diff] [blame] | 79 | #define CONFIG_PARTITION_UUIDS |
Stephen Warren | 11d9c03 | 2013-02-28 15:03:48 +0000 | [diff] [blame] | 80 | #define CONFIG_CMD_PART |
| 81 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 82 | #define CONFIG_SYS_NO_FLASH |
| 83 | |
| 84 | #define CONFIG_CONSOLE_MUX |
| 85 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV |
Stephen Warren | 86bd20b | 2015-04-14 08:41:14 -0600 | [diff] [blame] | 86 | #ifndef CONFIG_SPL_BUILD |
| 87 | #define CONFIG_SYS_STDIO_DEREGISTER |
| 88 | #endif |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 89 | |
| 90 | /* |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 91 | * Increasing the size of the IO buffer as default nfsargs size is more |
| 92 | * than 256 and so it is not possible to edit it |
| 93 | */ |
| 94 | #define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */ |
| 95 | /* Print Buffer Size */ |
| 96 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 97 | sizeof(CONFIG_SYS_PROMPT) + 16) |
Simon Glass | 0859b49 | 2015-06-05 14:39:40 -0600 | [diff] [blame] | 98 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 99 | /* Boot Argument Buffer Size */ |
| 100 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) |
| 101 | |
| 102 | #define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000) |
| 103 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) |
| 104 | |
Thierry Reding | 6527268 | 2015-07-27 11:45:26 -0600 | [diff] [blame] | 105 | #ifndef CONFIG_ARM64 |
Simon Glass | 9dacbb2 | 2014-11-10 17:16:42 -0700 | [diff] [blame] | 106 | #ifndef CONFIG_SPL_BUILD |
Marcel Ziswiler | 4270d5a | 2014-08-26 11:49:46 +0200 | [diff] [blame] | 107 | #define CONFIG_USE_ARCH_MEMCPY |
Simon Glass | 9dacbb2 | 2014-11-10 17:16:42 -0700 | [diff] [blame] | 108 | #endif |
Thierry Reding | 6527268 | 2015-07-27 11:45:26 -0600 | [diff] [blame] | 109 | #endif |
Marcel Ziswiler | 4270d5a | 2014-08-26 11:49:46 +0200 | [diff] [blame] | 110 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 111 | /*----------------------------------------------------------------------- |
| 112 | * Physical Memory Map |
| 113 | */ |
Stephen Warren | bbc1b99 | 2015-08-07 16:12:45 -0600 | [diff] [blame] | 114 | #define CONFIG_NR_DRAM_BANKS 2 |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 115 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
| 116 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ |
| 117 | |
| 118 | #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE |
| 119 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 120 | |
| 121 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ |
| 122 | |
| 123 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 124 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN |
| 125 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 126 | CONFIG_SYS_INIT_RAM_SIZE - \ |
| 127 | GENERATED_GBL_DATA_SIZE) |
| 128 | |
| 129 | #define CONFIG_TEGRA_GPIO |
| 130 | #define CONFIG_CMD_GPIO |
| 131 | #define CONFIG_CMD_ENTERRCM |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 132 | |
| 133 | /* Defines for SPL */ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 134 | #define CONFIG_SPL_FRAMEWORK |
| 135 | #define CONFIG_SPL_RAM_DEVICE |
| 136 | #define CONFIG_SPL_BOARD_INIT |
| 137 | #define CONFIG_SPL_NAND_SIMPLE |
Albert ARIBAUD | 6ebc346 | 2013-04-12 05:14:30 +0000 | [diff] [blame] | 138 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 139 | CONFIG_SPL_TEXT_BASE) |
| 140 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 |
| 141 | |
| 142 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 143 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
| 144 | #define CONFIG_SPL_SERIAL_SUPPORT |
| 145 | #define CONFIG_SPL_GPIO_SUPPORT |
| 146 | |
Simon Glass | dd7f65f | 2013-03-05 14:39:56 +0000 | [diff] [blame] | 147 | #define CONFIG_SYS_GENERIC_BOARD |
Stephen Warren | 026baff | 2015-01-19 16:25:51 -0700 | [diff] [blame] | 148 | #define CONFIG_BOARD_EARLY_INIT_F |
| 149 | #define CONFIG_BOARD_LATE_INIT |
Tom Warren | 3efff99 | 2013-03-26 10:39:33 -0700 | [diff] [blame] | 150 | |
Stephen Warren | a885f85 | 2013-02-28 15:03:45 +0000 | [diff] [blame] | 151 | /* Misc utility code */ |
| 152 | #define CONFIG_BOUNCE_BUFFER |
Tom Warren | 3efff99 | 2013-03-26 10:39:33 -0700 | [diff] [blame] | 153 | #define CONFIG_CRC32_VERIFY |
Simon Glass | dd7f65f | 2013-03-05 14:39:56 +0000 | [diff] [blame] | 154 | |
Stephen Warren | 68cf64d | 2014-02-05 09:24:57 -0700 | [diff] [blame] | 155 | #ifndef CONFIG_SPL_BUILD |
| 156 | #include <config_distro_defaults.h> |
| 157 | #endif |
| 158 | |
Tom Warren | f01b631 | 2012-12-11 13:34:18 +0000 | [diff] [blame] | 159 | #endif /* _TEGRA_COMMON_H_ */ |