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Priyanka Jain062ef1a2013-10-18 17:19:06 +05301/*
vijay raif4c39172014-03-31 11:46:34 +05302+ * Copyright 2014 Freescale Semiconductor, Inc.
3+ *
4+ * SPDX-License-Identifier: GPL-2.0+
5+ */
Priyanka Jain062ef1a2013-10-18 17:19:06 +05306
7#ifndef __CONFIG_H
8#define __CONFIG_H
9
10/*
vijay raif4c39172014-03-31 11:46:34 +053011 * T104x RDB board configuration file
Priyanka Jain062ef1a2013-10-18 17:19:06 +053012 */
13#define CONFIG_T104xRDB
Priyanka Jain062ef1a2013-10-18 17:19:06 +053014
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +053015#define CONFIG_E500 /* BOOKE e500 family */
16#include <asm/config_mpc85xx.h>
17
Priyanka Jain062ef1a2013-10-18 17:19:06 +053018#ifdef CONFIG_RAMBOOT_PBL
Sumit Gargaa36c842016-07-14 12:27:52 -040019
20#ifndef CONFIG_SECURE_BOOT
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053021#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi.cfg
Sumit Gargaa36c842016-07-14 12:27:52 -040022#else
23#define CONFIG_SYS_FSL_PBL_PBI \
24 $(SRCTREE)/board/freescale/t104xrdb/t104x_pbi_sb.cfg
25#endif
26
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053027#define CONFIG_SPL_FLUSH_IMAGE
28#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053029#define CONFIG_FSL_LAW /* Use common FSL init code */
Tang Yuantiance249d92014-07-23 17:27:53 +080030#define CONFIG_SYS_TEXT_BASE 0x30001000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053031#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
32#define CONFIG_SPL_PAD_TO 0x40000
33#define CONFIG_SPL_MAX_SIZE 0x28000
34#ifdef CONFIG_SPL_BUILD
35#define CONFIG_SPL_SKIP_RELOCATE
36#define CONFIG_SPL_COMMON_INIT_DDR
37#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
38#define CONFIG_SYS_NO_FLASH
39#endif
40#define RESET_VECTOR_OFFSET 0x27FFC
41#define BOOT_PAGE_OFFSET 0x27000
42
43#ifdef CONFIG_NAND
Sumit Gargaa36c842016-07-14 12:27:52 -040044#ifdef CONFIG_SECURE_BOOT
45#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
46/*
47 * HDR would be appended at end of image and copied to DDR along
48 * with U-Boot image.
49 */
50#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) + \
51 CONFIG_U_BOOT_HDR_SIZE)
52#else
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053053#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
Sumit Gargaa36c842016-07-14 12:27:52 -040054#endif
Tang Yuantiance249d92014-07-23 17:27:53 +080055#define CONFIG_SYS_NAND_U_BOOT_DST 0x30000000
56#define CONFIG_SYS_NAND_U_BOOT_START 0x30000000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053057#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
58#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Zhao Qiangec90ac72016-09-08 12:55:32 +080059#ifdef CONFIG_T1040RDB
60#define CONFIG_SYS_FSL_PBL_RCW \
61$(SRCTREE)/board/freescale/t104xrdb/t1040_nand_rcw.cfg
62#endif
63#ifdef CONFIG_T1042RDB_PI
64#define CONFIG_SYS_FSL_PBL_RCW \
65$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_nand_rcw.cfg
66#endif
67#ifdef CONFIG_T1042RDB
68#define CONFIG_SYS_FSL_PBL_RCW \
69$(SRCTREE)/board/freescale/t104xrdb/t1042_nand_rcw.cfg
70#endif
York Suna0167352016-11-21 10:46:53 -080071#ifdef CONFIG_TARGET_T1040D4RDB
Zhao Qiangec90ac72016-09-08 12:55:32 +080072#define CONFIG_SYS_FSL_PBL_RCW \
73$(SRCTREE)/board/freescale/t104xrdb/t1040d4_nand_rcw.cfg
74#endif
75#ifdef CONFIG_T1042D4RDB
76#define CONFIG_SYS_FSL_PBL_RCW \
77$(SRCTREE)/board/freescale/t104xrdb/t1042d4_nand_rcw.cfg
78#endif
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053079#define CONFIG_SPL_NAND_BOOT
80#endif
81
82#ifdef CONFIG_SPIFLASH
Tang Yuantiance249d92014-07-23 17:27:53 +080083#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053084#define CONFIG_SPL_SPI_FLASH_MINIMAL
85#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Tang Yuantiance249d92014-07-23 17:27:53 +080086#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x30000000)
87#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x30000000)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +053088#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
89#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90#ifndef CONFIG_SPL_BUILD
91#define CONFIG_SYS_MPC85XX_NO_RESETVEC
92#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080093#ifdef CONFIG_T1040RDB
94#define CONFIG_SYS_FSL_PBL_RCW \
95$(SRCTREE)/board/freescale/t104xrdb/t1040_spi_rcw.cfg
96#endif
97#ifdef CONFIG_T1042RDB_PI
98#define CONFIG_SYS_FSL_PBL_RCW \
99$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_spi_rcw.cfg
100#endif
101#ifdef CONFIG_T1042RDB
102#define CONFIG_SYS_FSL_PBL_RCW \
103$(SRCTREE)/board/freescale/t104xrdb/t1042_spi_rcw.cfg
104#endif
York Suna0167352016-11-21 10:46:53 -0800105#ifdef CONFIG_TARGET_T1040D4RDB
Zhao Qiangec90ac72016-09-08 12:55:32 +0800106#define CONFIG_SYS_FSL_PBL_RCW \
107$(SRCTREE)/board/freescale/t104xrdb/t1040d4_spi_rcw.cfg
108#endif
109#ifdef CONFIG_T1042D4RDB
110#define CONFIG_SYS_FSL_PBL_RCW \
111$(SRCTREE)/board/freescale/t104xrdb/t1042d4_spi_rcw.cfg
112#endif
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530113#define CONFIG_SPL_SPI_BOOT
114#endif
115
116#ifdef CONFIG_SDCARD
Tang Yuantiance249d92014-07-23 17:27:53 +0800117#define CONFIG_RESET_VECTOR_ADDRESS 0x30000FFC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530118#define CONFIG_SPL_MMC_MINIMAL
119#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Tang Yuantiance249d92014-07-23 17:27:53 +0800120#define CONFIG_SYS_MMC_U_BOOT_DST (0x30000000)
121#define CONFIG_SYS_MMC_U_BOOT_START (0x30000000)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530122#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
123#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
124#ifndef CONFIG_SPL_BUILD
125#define CONFIG_SYS_MPC85XX_NO_RESETVEC
126#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +0800127#ifdef CONFIG_T1040RDB
128#define CONFIG_SYS_FSL_PBL_RCW \
129$(SRCTREE)/board/freescale/t104xrdb/t1040_sd_rcw.cfg
130#endif
131#ifdef CONFIG_T1042RDB_PI
132#define CONFIG_SYS_FSL_PBL_RCW \
133$(SRCTREE)/board/freescale/t104xrdb/t1042_pi_sd_rcw.cfg
134#endif
135#ifdef CONFIG_T1042RDB
136#define CONFIG_SYS_FSL_PBL_RCW \
137$(SRCTREE)/board/freescale/t104xrdb/t1042_sd_rcw.cfg
138#endif
York Suna0167352016-11-21 10:46:53 -0800139#ifdef CONFIG_TARGET_T1040D4RDB
Zhao Qiangec90ac72016-09-08 12:55:32 +0800140#define CONFIG_SYS_FSL_PBL_RCW \
141$(SRCTREE)/board/freescale/t104xrdb/t1040d4_sd_rcw.cfg
142#endif
143#ifdef CONFIG_T1042D4RDB
144#define CONFIG_SYS_FSL_PBL_RCW \
145$(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
146#endif
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530147#define CONFIG_SPL_MMC_BOOT
148#endif
149
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530150#endif
151
152/* High Level Configuration Options */
153#define CONFIG_BOOKE
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530154#define CONFIG_E500MC /* BOOKE e500mc family */
155#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530156#define CONFIG_MP /* support multiple processors */
157
Tang Yuantian5303a3d2014-04-17 15:33:45 +0800158/* support deep sleep */
159#define CONFIG_DEEP_SLEEP
Tang Yuantian00233522014-11-21 11:17:16 +0800160#if defined(CONFIG_DEEP_SLEEP)
161#define CONFIG_BOARD_EARLY_INIT_F
Tang Yuantian00233522014-11-21 11:17:16 +0800162#endif
Tang Yuantian5303a3d2014-04-17 15:33:45 +0800163
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530164#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530165#define CONFIG_SYS_TEXT_BASE 0xeff40000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530166#endif
167
168#ifndef CONFIG_RESET_VECTOR_ADDRESS
169#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
170#endif
171
172#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
173#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
174#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +0530175#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530176#define CONFIG_PCI_INDIRECT_BRIDGE
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400177#define CONFIG_PCIE1 /* PCIE controller 1 */
178#define CONFIG_PCIE2 /* PCIE controller 2 */
179#define CONFIG_PCIE3 /* PCIE controller 3 */
180#define CONFIG_PCIE4 /* PCIE controller 4 */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530181
182#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
183#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
184
185#define CONFIG_FSL_LAW /* Use common FSL init code */
186
187#define CONFIG_ENV_OVERWRITE
188
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530189#ifndef CONFIG_SYS_NO_FLASH
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530190#define CONFIG_FLASH_CFI_DRIVER
191#define CONFIG_SYS_FLASH_CFI
192#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
193#endif
194
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530195#if defined(CONFIG_SPIFLASH)
196#define CONFIG_SYS_EXTRA_ENV_RELOC
197#define CONFIG_ENV_IS_IN_SPI_FLASH
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530198#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
199#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
200#define CONFIG_ENV_SECT_SIZE 0x10000
201#elif defined(CONFIG_SDCARD)
202#define CONFIG_SYS_EXTRA_ENV_RELOC
203#define CONFIG_ENV_IS_IN_MMC
204#define CONFIG_SYS_MMC_ENV_DEV 0
205#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530206#define CONFIG_ENV_OFFSET (512 * 0x800)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530207#elif defined(CONFIG_NAND)
Sumit Gargaa36c842016-07-14 12:27:52 -0400208#ifdef CONFIG_SECURE_BOOT
209#define CONFIG_RAMBOOT_NAND
210#define CONFIG_BOOTSCRIPT_COPY_RAM
211#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530212#define CONFIG_SYS_EXTRA_ENV_RELOC
213#define CONFIG_ENV_IS_IN_NAND
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530214#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530215#define CONFIG_ENV_OFFSET (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530216#else
217#define CONFIG_ENV_IS_IN_FLASH
218#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
219#define CONFIG_ENV_SIZE 0x2000
220#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
221#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530222
223#define CONFIG_SYS_CLK_FREQ 100000000
224#define CONFIG_DDR_CLK_FREQ 66666666
225
226/*
227 * These can be toggled for performance analysis, otherwise use default.
228 */
229#define CONFIG_SYS_CACHE_STASHING
230#define CONFIG_BACKSIDE_L2_CACHE
231#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
232#define CONFIG_BTB /* toggle branch predition */
233#define CONFIG_DDR_ECC
234#ifdef CONFIG_DDR_ECC
235#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
236#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
237#endif
238
239#define CONFIG_ENABLE_36BIT_PHYS
240
241#define CONFIG_ADDR_MAP
242#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
243
244#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
245#define CONFIG_SYS_MEMTEST_END 0x00400000
246#define CONFIG_SYS_ALT_MEMTEST
247#define CONFIG_PANIC_HANG /* do not reset board on panic */
248
249/*
250 * Config the L3 Cache as L3 SRAM
251 */
252#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
Sumit Gargaa36c842016-07-14 12:27:52 -0400253/*
254 * For Secure Boot CONFIG_SYS_INIT_L3_ADDR will be redefined and hence
255 * Physical address (CONFIG_SYS_INIT_L3_ADDR) and virtual address
256 * (CONFIG_SYS_INIT_L3_VADDR) will be different.
257 */
258#define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530259#define CONFIG_SYS_L3_SIZE 256 << 10
Sumit Gargaa36c842016-07-14 12:27:52 -0400260#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_VADDR + 32 * 1024)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530261#ifdef CONFIG_RAMBOOT_PBL
262#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
263#endif
264#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
265#define CONFIG_SPL_RELOC_MALLOC_SIZE (30 << 10)
266#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
267#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530268
269#define CONFIG_SYS_DCSRBAR 0xf0000000
270#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
271
272/*
273 * DDR Setup
274 */
275#define CONFIG_VERY_BIG_RAM
276#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
277#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
278
279/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
280#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain96ac18c2014-02-26 09:38:37 +0530281#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530282
283#define CONFIG_DDR_SPD
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530284#ifndef CONFIG_SYS_FSL_DDR4
York Sun5614e712013-09-30 09:22:09 -0700285#define CONFIG_SYS_FSL_DDR3
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530286#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530287
288#define CONFIG_SYS_SPD_BUS_NUM 0
289#define SPD_EEPROM_ADDRESS 0x51
290
291#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
292
293/*
294 * IFC Definitions
295 */
296#define CONFIG_SYS_FLASH_BASE 0xe8000000
297#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
298
299#define CONFIG_SYS_NOR_CSPR_EXT (0xf)
300#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE) | \
301 CSPR_PORT_SIZE_16 | \
302 CSPR_MSEL_NOR | \
303 CSPR_V)
304#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530305
306/*
307 * TDM Definition
308 */
309#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
310
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530311/* NOR Flash Timing Params */
312#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
313#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
314 FTIM0_NOR_TEADC(0x5) | \
315 FTIM0_NOR_TEAHC(0x5))
316#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
317 FTIM1_NOR_TRAD_NOR(0x1A) |\
318 FTIM1_NOR_TSEQRAD_NOR(0x13))
319#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
320 FTIM2_NOR_TCH(0x4) | \
321 FTIM2_NOR_TWPH(0x0E) | \
322 FTIM2_NOR_TWP(0x1c))
323#define CONFIG_SYS_NOR_FTIM3 0x0
324
325#define CONFIG_SYS_FLASH_QUIET_TEST
326#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
327
328#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
329#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
330#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
331#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
332
333#define CONFIG_SYS_FLASH_EMPTY_INFO
334#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
335
336/* CPLD on IFC */
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +0530337#define CPLD_LBMAP_MASK 0x3F
338#define CPLD_BANK_SEL_MASK 0x07
339#define CPLD_BANK_OVERRIDE 0x40
340#define CPLD_LBMAP_ALTBANK 0x44 /* BANK OR | BANK 4 */
341#define CPLD_LBMAP_DFLTBANK 0x40 /* BANK OR | BANK0 */
342#define CPLD_LBMAP_RESET 0xFF
343#define CPLD_LBMAP_SHIFT 0x03
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530344
345#if defined(CONFIG_T1042RDB_PI)
Jason Jincf8ddac2014-03-19 10:47:56 +0800346#define CPLD_DIU_SEL_DFP 0x80
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530347#elif defined(CONFIG_T1042D4RDB)
348#define CPLD_DIU_SEL_DFP 0xc0
349#endif
350
York Suna0167352016-11-21 10:46:53 -0800351#if defined(CONFIG_TARGET_T1040D4RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530352#define CPLD_INT_MASK_ALL 0xFF
353#define CPLD_INT_MASK_THERM 0x80
354#define CPLD_INT_MASK_DVI_DFP 0x40
355#define CPLD_INT_MASK_QSGMII1 0x20
356#define CPLD_INT_MASK_QSGMII2 0x10
357#define CPLD_INT_MASK_SGMI1 0x08
358#define CPLD_INT_MASK_SGMI2 0x04
359#define CPLD_INT_MASK_TDMR1 0x02
360#define CPLD_INT_MASK_TDMR2 0x01
Jason Jincf8ddac2014-03-19 10:47:56 +0800361#endif
Prabhakar Kushwaha55153d62014-04-03 16:50:05 +0530362
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530363#define CONFIG_SYS_CPLD_BASE 0xffdf0000
364#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
Priyanka Jain9b444be2014-01-27 14:07:11 +0530365#define CONFIG_SYS_CSPR2_EXT (0xf)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530366#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \
367 | CSPR_PORT_SIZE_8 \
368 | CSPR_MSEL_GPCM \
369 | CSPR_V)
370#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
371#define CONFIG_SYS_CSOR2 0x0
372/* CPLD Timing parameters for IFC CS2 */
373#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
374 FTIM0_GPCM_TEADC(0x0e) | \
375 FTIM0_GPCM_TEAHC(0x0e))
376#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
377 FTIM1_GPCM_TRAD(0x1f))
378#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800379 FTIM2_GPCM_TCH(0x8) | \
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530380 FTIM2_GPCM_TWP(0x1f))
381#define CONFIG_SYS_CS2_FTIM3 0x0
382
383/* NAND Flash on IFC */
384#define CONFIG_NAND_FSL_IFC
385#define CONFIG_SYS_NAND_BASE 0xff800000
386#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
387
388#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
389#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
390 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
391 | CSPR_MSEL_NAND /* MSEL = NAND */ \
392 | CSPR_V)
393#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
394
395#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
396 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
397 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
398 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
399 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
400 | CSOR_NAND_SPRZ_224/* Spare size = 224 */ \
401 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
402
403#define CONFIG_SYS_NAND_ONFI_DETECTION
404
405/* ONFI NAND Flash mode0 Timing Params */
406#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
407 FTIM0_NAND_TWP(0x18) | \
408 FTIM0_NAND_TWCHT(0x07) | \
409 FTIM0_NAND_TWH(0x0a))
410#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
411 FTIM1_NAND_TWBE(0x39) | \
412 FTIM1_NAND_TRR(0x0e) | \
413 FTIM1_NAND_TRP(0x18))
414#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
415 FTIM2_NAND_TREH(0x0a) | \
416 FTIM2_NAND_TWHRE(0x1e))
417#define CONFIG_SYS_NAND_FTIM3 0x0
418
419#define CONFIG_SYS_NAND_DDR_LAW 11
420#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
421#define CONFIG_SYS_MAX_NAND_DEVICE 1
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530422#define CONFIG_CMD_NAND
423
424#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
425
426#if defined(CONFIG_NAND)
427#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
428#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
429#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
430#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
431#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
432#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
433#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
434#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
435#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR_CSPR_EXT
436#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR
437#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
438#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
439#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
440#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
441#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
442#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
443#else
444#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR_CSPR_EXT
445#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR
446#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
447#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
448#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
449#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
450#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
451#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
452#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
453#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
454#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
455#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
456#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
457#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
458#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
459#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
460#endif
461
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530462#ifdef CONFIG_SPL_BUILD
463#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
464#else
465#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
466#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530467
468#if defined(CONFIG_RAMBOOT_PBL)
469#define CONFIG_SYS_RAMBOOT
470#endif
471
Prabhakar Kushwaha9f074e62014-10-29 22:33:09 +0530472#ifdef CONFIG_SYS_FSL_ERRATUM_A008044
473#if defined(CONFIG_NAND)
474#define CONFIG_A008044_WORKAROUND
475#endif
476#endif
477
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530478#define CONFIG_BOARD_EARLY_INIT_R
479#define CONFIG_MISC_INIT_R
480
481#define CONFIG_HWCONFIG
482
483/* define to use L1 as initial stack */
484#define CONFIG_L1_INIT_RAM
485#define CONFIG_SYS_INIT_RAM_LOCK
486#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
487#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700488#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530489/* The assembler doesn't like typecast */
490#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
491 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
492 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
493#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
494
495#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
496 GENERATED_GBL_DATA_SIZE)
497#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
498
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530499#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530500#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
501
502/* Serial Port - controlled on board with jumper J8
503 * open - index 2
504 * shorted - index 1
505 */
506#define CONFIG_CONS_INDEX 1
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530507#define CONFIG_SYS_NS16550_SERIAL
508#define CONFIG_SYS_NS16550_REG_SIZE 1
509#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
510
511#define CONFIG_SYS_BAUDRATE_TABLE \
512 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
513
514#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
515#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
516#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
517#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530518
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530519#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T1042D4RDB)
Jason Jincf8ddac2014-03-19 10:47:56 +0800520/* Video */
521#define CONFIG_FSL_DIU_FB
522
523#ifdef CONFIG_FSL_DIU_FB
524#define CONFIG_FSL_DIU_CH7301
525#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
Jason Jincf8ddac2014-03-19 10:47:56 +0800526#define CONFIG_CMD_BMP
Jason Jincf8ddac2014-03-19 10:47:56 +0800527#define CONFIG_VIDEO_LOGO
528#define CONFIG_VIDEO_BMP_LOGO
529#endif
530#endif
531
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530532/* I2C */
533#define CONFIG_SYS_I2C
534#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
535#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800536#define CONFIG_SYS_FSL_I2C2_SPEED 400000
537#define CONFIG_SYS_FSL_I2C3_SPEED 400000
538#define CONFIG_SYS_FSL_I2C4_SPEED 400000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530539#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530540#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800541#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
542#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530543#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800544#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
545#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
546#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530547
548/* I2C bus multiplexer */
549#define I2C_MUX_PCA_ADDR 0x70
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530550#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530551#define I2C_MUX_CH_DEFAULT 0x8
vijay raif4c39172014-03-31 11:46:34 +0530552#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530553
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530554#if defined(CONFIG_T1042RDB_PI) || defined(CONFIG_T104XD4RDB)
Jason Jincf8ddac2014-03-19 10:47:56 +0800555/* LDI/DVI Encoder for display */
556#define CONFIG_SYS_I2C_LDI_ADDR 0x38
557#define CONFIG_SYS_I2C_DVI_ADDR 0x75
558
vijay raif4c39172014-03-31 11:46:34 +0530559/*
560 * RTC configuration
561 */
562#define RTC
563#define CONFIG_RTC_DS1337 1
564#define CONFIG_SYS_I2C_RTC_ADDR 0x68
565
566/*DVI encoder*/
567#define CONFIG_HDMI_ENCODER_I2C_ADDR 0x75
568#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530569
570/*
571 * eSPI - Enhanced SPI
572 */
Zhiqiang Hou7172de32014-09-17 17:37:44 +0800573#define CONFIG_SPI_FLASH_BAR
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530574#define CONFIG_SF_DEFAULT_SPEED 10000000
575#define CONFIG_SF_DEFAULT_MODE 0
Priyanka Jain9b444be2014-01-27 14:07:11 +0530576#define CONFIG_ENV_SPI_BUS 0
577#define CONFIG_ENV_SPI_CS 0
578#define CONFIG_ENV_SPI_MAX_HZ 10000000
579#define CONFIG_ENV_SPI_MODE 0
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530580
581/*
582 * General PCI
583 * Memory space is mapped 1-1, but I/O space must start from 0.
584 */
585
586#ifdef CONFIG_PCI
587/* controller 1, direct to uli, tgtid 3, Base address 20000 */
588#ifdef CONFIG_PCIE1
589#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
590#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
591#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
592#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
593#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
594#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
595#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
596#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
597#endif
598
599/* controller 2, Slot 2, tgtid 2, Base address 201000 */
600#ifdef CONFIG_PCIE2
601#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
602#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
603#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
604#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
605#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
606#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
607#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
608#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
609#endif
610
611/* controller 3, Slot 1, tgtid 1, Base address 202000 */
612#ifdef CONFIG_PCIE3
613#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
614#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
615#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
616#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
617#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
618#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
619#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
620#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
621#endif
622
623/* controller 4, Base address 203000 */
624#ifdef CONFIG_PCIE4
625#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
626#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
627#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
628#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
629#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
630#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
631#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
632#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
633#endif
634
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530635#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
636#define CONFIG_DOS_PARTITION
637#endif /* CONFIG_PCI */
638
639/* SATA */
640#define CONFIG_FSL_SATA_V2
641#ifdef CONFIG_FSL_SATA_V2
642#define CONFIG_LIBATA
643#define CONFIG_FSL_SATA
644
645#define CONFIG_SYS_SATA_MAX_DEVICE 1
646#define CONFIG_SATA1
647#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
648#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
649
650#define CONFIG_LBA48
651#define CONFIG_CMD_SATA
652#define CONFIG_DOS_PARTITION
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530653#endif
654
655/*
656* USB
657*/
658#define CONFIG_HAS_FSL_DR_USB
659
660#ifdef CONFIG_HAS_FSL_DR_USB
661#define CONFIG_USB_EHCI
662
663#ifdef CONFIG_USB_EHCI
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530664#define CONFIG_USB_EHCI_FSL
665#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530666#endif
667#endif
668
669#define CONFIG_MMC
670
671#ifdef CONFIG_MMC
672#define CONFIG_FSL_ESDHC
673#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530674#define CONFIG_GENERIC_MMC
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530675#define CONFIG_DOS_PARTITION
676#endif
677
678/* Qman/Bman */
679#ifndef CONFIG_NOBQFMAN
680#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500681#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530682#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
683#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
684#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500685#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
686#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
687#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
688#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
689#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
690 CONFIG_SYS_BMAN_CENA_SIZE)
691#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
692#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500693#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530694#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
695#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
696#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500697#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
698#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
699#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
700#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
701#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
702 CONFIG_SYS_QMAN_CENA_SIZE)
703#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
704#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530705
706#define CONFIG_SYS_DPAA_FMAN
707#define CONFIG_SYS_DPAA_PME
708
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530709#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800710#define CONFIG_QE
711#define CONFIG_U_QE
Prabhakar Kushwaha099b86b2014-04-21 10:47:25 +0530712#endif
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800713
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530714/* Default address of microcode for the Linux Fman driver */
715#if defined(CONFIG_SPIFLASH)
716/*
717 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
718 * env, so we got 0x110000.
719 */
720#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800721#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530722#elif defined(CONFIG_SDCARD)
723/*
724 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530725 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
726 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530727 */
728#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530729#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530730#elif defined(CONFIG_NAND)
731#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530732#define CONFIG_SYS_FMAN_FW_ADDR (5 * CONFIG_SYS_NAND_BLOCK_SIZE)
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530733#else
734#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800735#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530736#endif
737
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530738#if defined(CONFIG_T104xRDB) || defined(CONFIG_T104XD4RDB)
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530739#if defined(CONFIG_SPIFLASH)
740#define CONFIG_SYS_QE_FW_ADDR 0x130000
741#elif defined(CONFIG_SDCARD)
742#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
743#elif defined(CONFIG_NAND)
744#define CONFIG_SYS_QE_FW_ADDR (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
745#else
Zhao Qiang59ff5d32014-03-14 10:11:03 +0800746#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530747#endif
Prabhakar Kushwaha18c01442014-04-08 19:13:56 +0530748#endif
749
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530750#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
751#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
752#endif /* CONFIG_NOBQFMAN */
753
754#ifdef CONFIG_SYS_DPAA_FMAN
755#define CONFIG_FMAN_ENET
756#define CONFIG_PHY_VITESSE
757#define CONFIG_PHY_REALTEK
758#endif
759
760#ifdef CONFIG_FMAN_ENET
vijay rai363fb322014-08-19 12:46:53 +0530761#if defined(CONFIG_T1040RDB) || defined(CONFIG_T1042RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530762#define CONFIG_SYS_SGMII1_PHY_ADDR 0x03
York Suna0167352016-11-21 10:46:53 -0800763#elif defined(CONFIG_TARGET_T1040D4RDB)
Codrin Ciubotariu94af6842015-10-12 16:33:13 +0300764#define CONFIG_SYS_SGMII1_PHY_ADDR 0x01
765#elif defined(CONFIG_T1042D4RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530766#define CONFIG_SYS_SGMII1_PHY_ADDR 0x02
767#define CONFIG_SYS_SGMII2_PHY_ADDR 0x03
768#define CONFIG_SYS_SGMII3_PHY_ADDR 0x01
vijay raif4c39172014-03-31 11:46:34 +0530769#endif
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530770
771#ifdef CONFIG_T104XD4RDB
772#define CONFIG_SYS_RGMII1_PHY_ADDR 0x04
773#define CONFIG_SYS_RGMII2_PHY_ADDR 0x05
774#else
775#define CONFIG_SYS_RGMII1_PHY_ADDR 0x01
776#define CONFIG_SYS_RGMII2_PHY_ADDR 0x02
777#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530778
Codrin Ciubotariudb4a1762015-01-21 11:54:12 +0200779/* Enable VSC9953 L2 Switch driver on T1040 SoC */
York Suna0167352016-11-21 10:46:53 -0800780#if defined(CONFIG_T1040RDB) || defined(CONFIG_TARGET_T1040D4RDB)
Codrin Ciubotariudb4a1762015-01-21 11:54:12 +0200781#define CONFIG_VSC9953
Codrin Ciubotariu24a23de2015-07-24 16:55:28 +0300782#define CONFIG_CMD_ETHSW
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530783#ifdef CONFIG_T1040RDB
Codrin Ciubotariudb4a1762015-01-21 11:54:12 +0200784#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x04
785#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x08
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530786#else
787#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x08
788#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x0c
789#endif
Codrin Ciubotariudb4a1762015-01-21 11:54:12 +0200790#endif
791
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530792#define CONFIG_MII /* MII PHY management */
Priyanka Jain714fd402014-01-30 11:30:04 +0530793#define CONFIG_ETHPRIME "FM1@DTSEC4"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530794#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
795#endif
796
797/*
798 * Environment
799 */
800#define CONFIG_LOADS_ECHO /* echo on for serial download */
801#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
802
803/*
804 * Command line configuration.
805 */
vijay raif4c39172014-03-31 11:46:34 +0530806#ifdef CONFIG_T1042RDB_PI
807#define CONFIG_CMD_DATE
808#endif
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530809#define CONFIG_CMD_ERRATA
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530810#define CONFIG_CMD_IRQ
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530811#define CONFIG_CMD_REGINFO
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530812
813#ifdef CONFIG_PCI
814#define CONFIG_CMD_PCI
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530815#endif
816
Ruchika Gupta737537e2014-10-15 11:35:31 +0530817/* Hash command with SHA acceleration supported in hardware */
818#ifdef CONFIG_FSL_CAAM
819#define CONFIG_CMD_HASH
820#define CONFIG_SHA_HW_ACCEL
821#endif
822
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530823/*
824 * Miscellaneous configurable options
825 */
826#define CONFIG_SYS_LONGHELP /* undef to save memory */
827#define CONFIG_CMDLINE_EDITING /* Command-line editing */
828#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
829#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530830#ifdef CONFIG_CMD_KGDB
831#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
832#else
833#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
834#endif
835#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
836#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
837#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530838
839/*
840 * For booting Linux, the board info and command line data
841 * have to be in the first 64 MB of memory, since this is
842 * the maximum mapped by the Linux kernel during initialization.
843 */
844#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
845#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
846
847#ifdef CONFIG_CMD_KGDB
848#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530849#endif
850
851/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530852 * Dynamic MTD Partition support with mtdparts
853 */
854#ifndef CONFIG_SYS_NO_FLASH
855#define CONFIG_MTD_DEVICE
856#define CONFIG_MTD_PARTITIONS
857#define CONFIG_CMD_MTDPARTS
858#define CONFIG_FLASH_CFI_MTD
859#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
860 "spi0=spife110000.0"
861#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
862 "128k(dtb),96m(fs),-(user);"\
863 "fff800000.flash:2m(uboot),9m(kernel),"\
864 "128k(dtb),96m(fs),-(user);spife110000.0:" \
865 "2m(uboot),9m(kernel),128k(dtb),-(user)"
866#endif
867
868/*
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530869 * Environment Configuration
870 */
871#define CONFIG_ROOTPATH "/opt/nfsroot"
872#define CONFIG_BOOTFILE "uImage"
873#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
874
875/* default location for tftp and bootm */
876#define CONFIG_LOADADDR 1000000
877
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530878
879#define CONFIG_BAUDRATE 115200
880
881#define __USB_PHY_TYPE utmi
vijay rai363fb322014-08-19 12:46:53 +0530882#define RAMDISKFILE "t104xrdb/ramdisk.uboot"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530883
vijay raif4c39172014-03-31 11:46:34 +0530884#ifdef CONFIG_T1040RDB
885#define FDTFILE "t1040rdb/t1040rdb.dtb"
vijay rai363fb322014-08-19 12:46:53 +0530886#elif defined(CONFIG_T1042RDB_PI)
887#define FDTFILE "t1042rdb_pi/t1042rdb_pi.dtb"
888#elif defined(CONFIG_T1042RDB)
889#define FDTFILE "t1042rdb/t1042rdb.dtb"
York Suna0167352016-11-21 10:46:53 -0800890#elif defined(CONFIG_TARGET_T1040D4RDB)
Priyanka Jain4b6067a2015-06-05 15:29:02 +0530891#define FDTFILE "t1042rdb/t1040d4rdb.dtb"
892#elif defined(CONFIG_T1042D4RDB)
893#define FDTFILE "t1042rdb/t1042d4rdb.dtb"
vijay raif4c39172014-03-31 11:46:34 +0530894#endif
895
Jason Jincf8ddac2014-03-19 10:47:56 +0800896#ifdef CONFIG_FSL_DIU_FB
897#define DIU_ENVIRONMENT "video-mode=fslfb:1024x768-32@60,monitor=dvi"
898#else
899#define DIU_ENVIRONMENT
900#endif
901
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530902#define CONFIG_EXTRA_ENV_SETTINGS \
Priyanka Jain9b444be2014-01-27 14:07:11 +0530903 "hwconfig=fsl_ddr:bank_intlv=cs0_cs1;" \
904 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
905 "usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530906 "netdev=eth0\0" \
Jason Jincf8ddac2014-03-19 10:47:56 +0800907 "video-mode=" __stringify(DIU_ENVIRONMENT) "\0" \
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530908 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
909 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
910 "tftpflash=tftpboot $loadaddr $uboot && " \
911 "protect off $ubootaddr +$filesize && " \
912 "erase $ubootaddr +$filesize && " \
913 "cp.b $loadaddr $ubootaddr $filesize && " \
914 "protect on $ubootaddr +$filesize && " \
915 "cmp.b $loadaddr $ubootaddr $filesize\0" \
916 "consoledev=ttyS0\0" \
917 "ramdiskaddr=2000000\0" \
vijay raif4c39172014-03-31 11:46:34 +0530918 "ramdiskfile=" __stringify(RAMDISKFILE) "\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500919 "fdtaddr=1e00000\0" \
vijay raif4c39172014-03-31 11:46:34 +0530920 "fdtfile=" __stringify(FDTFILE) "\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500921 "bdev=sda3\0"
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530922
923#define CONFIG_LINUX \
924 "setenv bootargs root=/dev/ram rw " \
925 "console=$consoledev,$baudrate $othbootargs;" \
926 "setenv ramdiskaddr 0x02000000;" \
927 "setenv fdtaddr 0x00c00000;" \
928 "setenv loadaddr 0x1000000;" \
929 "bootm $loadaddr $ramdiskaddr $fdtaddr"
930
931#define CONFIG_HDBOOT \
932 "setenv bootargs root=/dev/$bdev rw " \
933 "console=$consoledev,$baudrate $othbootargs;" \
934 "tftp $loadaddr $bootfile;" \
935 "tftp $fdtaddr $fdtfile;" \
936 "bootm $loadaddr - $fdtaddr"
937
938#define CONFIG_NFSBOOTCOMMAND \
939 "setenv bootargs root=/dev/nfs rw " \
940 "nfsroot=$serverip:$rootpath " \
941 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
942 "console=$consoledev,$baudrate $othbootargs;" \
943 "tftp $loadaddr $bootfile;" \
944 "tftp $fdtaddr $fdtfile;" \
945 "bootm $loadaddr - $fdtaddr"
946
947#define CONFIG_RAMBOOTCOMMAND \
948 "setenv bootargs root=/dev/ram rw " \
949 "console=$consoledev,$baudrate $othbootargs;" \
950 "tftp $ramdiskaddr $ramdiskfile;" \
951 "tftp $loadaddr $bootfile;" \
952 "tftp $fdtaddr $fdtfile;" \
953 "bootm $loadaddr $ramdiskaddr $fdtaddr"
954
955#define CONFIG_BOOTCOMMAND CONFIG_LINUX
956
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530957#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530958
Priyanka Jain062ef1a2013-10-18 17:19:06 +0530959#endif /* __CONFIG_H */