| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 1 | /* |
| 2 | * blackfin-config-post.h - setup common defines for Blackfin boards based on config.h |
| 3 | * |
| 4 | * Copyright (c) 2007 Analog Devices Inc. |
| 5 | * |
| 6 | * Licensed under the GPL-2 or later. |
| 7 | */ |
| 8 | |
| 9 | #ifndef __ASM_BLACKFIN_CONFIG_POST_H__ |
| 10 | #define __ASM_BLACKFIN_CONFIG_POST_H__ |
| 11 | |
| 12 | /* Check to make sure everything fits in external RAM */ |
| Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 13 | #if ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE) |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 14 | # error Memory Map does not fit into configuration |
| 15 | #endif |
| 16 | |
| Mike Frysinger | 9171fc8 | 2008-03-30 15:46:13 -0400 | [diff] [blame] | 17 | /* Sanity check CONFIG_BFIN_CPU */ |
| 18 | #ifndef CONFIG_BFIN_CPU |
| 19 | # error CONFIG_BFIN_CPU: your board config needs to define this |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 20 | #endif |
| 21 | |
| 22 | /* Make sure the structure is properly aligned */ |
| Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 23 | #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR) |
| 24 | # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned |
| Mike Frysinger | d4d7730 | 2008-02-04 19:26:55 -0500 | [diff] [blame] | 25 | #endif |
| 26 | |
| 27 | /* Set default CONFIG_VCO_HZ if need be */ |
| 28 | #if !defined(CONFIG_VCO_HZ) |
| 29 | # if (CONFIG_CLKIN_HALF == 0) |
| 30 | # define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) |
| 31 | # else |
| 32 | # define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2) |
| 33 | # endif |
| 34 | #endif |
| 35 | |
| 36 | /* Set default CONFIG_CCLK_HZ if need be */ |
| 37 | #if !defined(CONFIG_CCLK_HZ) |
| 38 | # if (CONFIG_PLL_BYPASS == 0) |
| 39 | # define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV) |
| 40 | # else |
| 41 | # define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ |
| 42 | # endif |
| 43 | #endif |
| 44 | |
| 45 | /* Set default CONFIG_SCLK_HZ if need be */ |
| 46 | #if !defined(CONFIG_SCLK_HZ) |
| 47 | # if (CONFIG_PLL_BYPASS == 0) |
| 48 | # define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV) |
| 49 | # else |
| 50 | # define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ |
| 51 | # endif |
| 52 | #endif |
| 53 | |
| 54 | /* Since we use these to program PLL registers directly, |
| 55 | * make sure the values are sane and won't screw us up. |
| 56 | */ |
| 57 | #if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT |
| 58 | # error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63) |
| 59 | #endif |
| 60 | #if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF |
| 61 | # error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1 |
| 62 | #endif |
| 63 | #if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS |
| 64 | # error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1 |
| 65 | #endif |
| 66 | |
| 67 | /* Using L1 scratch pad makes sense for everyone by default. */ |
| 68 | #ifndef CMD_LINE_ADDR |
| 69 | # define CMD_LINE_ADDR L1_SRAM_SCRATCH |
| 70 | #endif |
| 71 | |
| 72 | #endif |