blob: 8d07061c36f36a67481484719ab44436eb4a9b02 [file] [log] [blame]
Jon Loeliger126aa702006-05-30 17:47:00 -05001/*
Timur Tabi2feb4af2010-03-31 17:44:13 -05002 * Copyright 2006,2010 Freescale Semiconductor
Jon Loeliger126aa702006-05-30 17:47:00 -05003 * Jeff Brown
4 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
Jon Loeliger126aa702006-05-30 17:47:00 -050026#include <command.h>
Andy Fleming5a8a1632008-08-31 16:33:30 -050027#include <asm/io.h>
Jon Loeligerad8f8682008-01-15 13:42:41 -060028
Timur Tabi2feb4af2010-03-31 17:44:13 -050029#define pixis_base (u8 *)PIXIS_BASE
Haiying Wang3d98b852007-01-22 12:37:30 -060030
31/*
32 * Simple board reset.
33 */
34void pixis_reset(void)
35{
Kumar Gala048e7ef2009-07-22 10:12:39 -050036 out_8(pixis_base + PIXIS_RST, 0);
Haiying Wang3d98b852007-01-22 12:37:30 -060037
Timur Tabi2feb4af2010-03-31 17:44:13 -050038 while (1);
39}
Haiying Wang3d98b852007-01-22 12:37:30 -060040
Jon Loeliger126aa702006-05-30 17:47:00 -050041/*
42 * Per table 27, page 58 of MPC8641HPCN spec.
43 */
Timur Tabi2feb4af2010-03-31 17:44:13 -050044static int set_px_sysclk(unsigned long sysclk)
Jon Loeliger126aa702006-05-30 17:47:00 -050045{
46 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
47
48 switch (sysclk) {
49 case 33:
50 sysclk_s = 0x04;
51 sysclk_r = 0x04;
52 sysclk_v = 0x07;
53 sysclk_aux = 0x00;
54 break;
55 case 40:
56 sysclk_s = 0x01;
57 sysclk_r = 0x1F;
58 sysclk_v = 0x20;
59 sysclk_aux = 0x01;
60 break;
61 case 50:
62 sysclk_s = 0x01;
63 sysclk_r = 0x1F;
64 sysclk_v = 0x2A;
65 sysclk_aux = 0x02;
66 break;
67 case 66:
68 sysclk_s = 0x01;
69 sysclk_r = 0x04;
70 sysclk_v = 0x04;
71 sysclk_aux = 0x03;
72 break;
73 case 83:
74 sysclk_s = 0x01;
75 sysclk_r = 0x1F;
76 sysclk_v = 0x4B;
77 sysclk_aux = 0x04;
78 break;
79 case 100:
80 sysclk_s = 0x01;
81 sysclk_r = 0x1F;
82 sysclk_v = 0x5C;
83 sysclk_aux = 0x05;
84 break;
85 case 134:
86 sysclk_s = 0x06;
87 sysclk_r = 0x1F;
88 sysclk_v = 0x3B;
89 sysclk_aux = 0x06;
90 break;
91 case 166:
92 sysclk_s = 0x06;
93 sysclk_r = 0x1F;
94 sysclk_v = 0x4B;
95 sysclk_aux = 0x07;
96 break;
97 default:
98 printf("Unsupported SYSCLK frequency.\n");
99 return 0;
100 }
101
Jon Loeliger80e955c2006-08-22 12:25:27 -0500102 vclkh = (sysclk_s << 5) | sysclk_r;
Jon Loeliger126aa702006-05-30 17:47:00 -0500103 vclkl = sysclk_v;
104
Kumar Gala048e7ef2009-07-22 10:12:39 -0500105 out_8(pixis_base + PIXIS_VCLKH, vclkh);
106 out_8(pixis_base + PIXIS_VCLKL, vclkl);
Jon Loeliger126aa702006-05-30 17:47:00 -0500107
Kumar Gala048e7ef2009-07-22 10:12:39 -0500108 out_8(pixis_base + PIXIS_AUX, sysclk_aux);
Jon Loeliger126aa702006-05-30 17:47:00 -0500109
110 return 1;
111}
112
Timur Tabi2feb4af2010-03-31 17:44:13 -0500113/* Set the CFG_SYSPLL bits
114 *
115 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
116 * read_from_px_regs() is called.
117 */
118static int set_px_mpxpll(unsigned long mpxpll)
Jon Loeliger126aa702006-05-30 17:47:00 -0500119{
Jon Loeliger126aa702006-05-30 17:47:00 -0500120 switch (mpxpll) {
121 case 2:
122 case 4:
123 case 6:
124 case 8:
125 case 10:
126 case 12:
127 case 14:
128 case 16:
Timur Tabi2feb4af2010-03-31 17:44:13 -0500129 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
130 return 1;
Jon Loeliger126aa702006-05-30 17:47:00 -0500131 }
132
Timur Tabi2feb4af2010-03-31 17:44:13 -0500133 printf("Unsupported MPXPLL ratio.\n");
134 return 0;
Jon Loeliger126aa702006-05-30 17:47:00 -0500135}
136
Timur Tabi2feb4af2010-03-31 17:44:13 -0500137static int set_px_corepll(unsigned long corepll)
Jon Loeliger126aa702006-05-30 17:47:00 -0500138{
Jon Loeliger126aa702006-05-30 17:47:00 -0500139 u8 val;
140
Timur Tabi2feb4af2010-03-31 17:44:13 -0500141 switch (corepll) {
Jon Loeliger126aa702006-05-30 17:47:00 -0500142 case 20:
143 val = 0x08;
144 break;
145 case 25:
146 val = 0x0C;
147 break;
148 case 30:
149 val = 0x10;
150 break;
151 case 35:
152 val = 0x1C;
153 break;
154 case 40:
155 val = 0x14;
156 break;
157 case 45:
158 val = 0x0E;
159 break;
160 default:
161 printf("Unsupported COREPLL ratio.\n");
162 return 0;
163 }
164
Timur Tabi2feb4af2010-03-31 17:44:13 -0500165 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
Jon Loeliger126aa702006-05-30 17:47:00 -0500166 return 1;
167}
168
Timur Tabi2feb4af2010-03-31 17:44:13 -0500169#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
170#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
171#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500172
Timur Tabi2feb4af2010-03-31 17:44:13 -0500173/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
174 *
175 * The PIXIS can be programmed to look at either the on-board dip switches
176 * or various other PIXIS registers to determine the values for COREPLL,
177 * MPXPLL, and SYSCLK.
178 *
179 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
180 * register that tells the pixis to use the various PIXIS register.
181 */
182static void read_from_px_regs(int set)
Jon Loeliger126aa702006-05-30 17:47:00 -0500183{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500184 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
Jon Loeliger126aa702006-05-30 17:47:00 -0500185
186 if (set)
Timur Tabi2feb4af2010-03-31 17:44:13 -0500187 tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
Jon Loeliger126aa702006-05-30 17:47:00 -0500188 else
Timur Tabi2feb4af2010-03-31 17:44:13 -0500189 tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
190
Kumar Gala048e7ef2009-07-22 10:12:39 -0500191 out_8(pixis_base + PIXIS_VCFGEN0, tmp);
Jon Loeliger126aa702006-05-30 17:47:00 -0500192}
193
Timur Tabi2feb4af2010-03-31 17:44:13 -0500194/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
195 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
196 */
197#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
198#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
199#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500200
Timur Tabi2feb4af2010-03-31 17:44:13 -0500201/* Configure the source of the boot location
202 *
203 * The PIXIS can be programmed to look at either the on-board dip switches
204 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
205 *
206 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
207 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
208 */
209static void read_from_px_regs_altbank(int set)
Jon Loeliger126aa702006-05-30 17:47:00 -0500210{
Kumar Gala048e7ef2009-07-22 10:12:39 -0500211 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500212
213 if (set)
Timur Tabi2feb4af2010-03-31 17:44:13 -0500214 tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
Jon Loeliger126aa702006-05-30 17:47:00 -0500215 else
Timur Tabi2feb4af2010-03-31 17:44:13 -0500216 tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
217
Kumar Gala048e7ef2009-07-22 10:12:39 -0500218 out_8(pixis_base + PIXIS_VCFGEN1, tmp);
Jon Loeliger126aa702006-05-30 17:47:00 -0500219}
220
Timur Tabi2feb4af2010-03-31 17:44:13 -0500221/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
222 * tells the PIXIS what the alternate flash bank is.
223 *
224 * Note that it's not really a mask. It contains the actual LBMAP bits that
225 * must be set to select the alternate bank. This code assumes that the
226 * primary bank has these bits set to 0, and the alternate bank has these
227 * bits set to 1.
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
230#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
Jason Jindb74b3c2007-10-29 19:26:21 +0800231#endif
Jon Loeliger126aa702006-05-30 17:47:00 -0500232
Timur Tabi2feb4af2010-03-31 17:44:13 -0500233/* Tell the PIXIS to boot from the default flash bank
234 *
235 * Program the default flash bank into the VBOOT register. This register is
236 * used only if PX_VCFGEN1[FLASH]=1.
237 */
238static void clear_altbank(void)
James Yang16c3cde2008-01-16 11:58:08 -0600239{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500240 clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
James Yang16c3cde2008-01-16 11:58:08 -0600241}
242
Timur Tabi2feb4af2010-03-31 17:44:13 -0500243/* Tell the PIXIS to boot from the alternate flash bank
244 *
245 * Program the alternate flash bank into the VBOOT register. This register is
246 * used only if PX_VCFGEN1[FLASH]=1.
247 */
248static void set_altbank(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500249{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500250 setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
Jon Loeliger126aa702006-05-30 17:47:00 -0500251}
252
Timur Tabi2feb4af2010-03-31 17:44:13 -0500253/* Reset the board with watchdog disabled.
254 *
255 * This respects the altbank setting.
256 */
257static void set_px_go(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500258{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500259 /* Disable the VELA sequencer and watchdog */
260 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500261
Timur Tabi2feb4af2010-03-31 17:44:13 -0500262 /* Reboot by starting the VELA sequencer */
263 setbits_8(pixis_base + PIXIS_VCTL, 0x1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500264
Timur Tabi2feb4af2010-03-31 17:44:13 -0500265 while (1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500266}
267
Timur Tabi2feb4af2010-03-31 17:44:13 -0500268/* Reset the board with watchdog enabled.
269 *
270 * This respects the altbank setting.
271 */
272static void set_px_go_with_watchdog(void)
Jon Loeliger126aa702006-05-30 17:47:00 -0500273{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500274 /* Disable the VELA sequencer */
275 clrbits_8(pixis_base + PIXIS_VCTL, 1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500276
Timur Tabi2feb4af2010-03-31 17:44:13 -0500277 /* Enable the watchdog and reboot by starting the VELA sequencer */
278 setbits_8(pixis_base + PIXIS_VCTL, 0x9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500279
Timur Tabi2feb4af2010-03-31 17:44:13 -0500280 while (1);
Jon Loeliger126aa702006-05-30 17:47:00 -0500281}
282
Timur Tabi2feb4af2010-03-31 17:44:13 -0500283/* Disable the watchdog
284 *
285 */
286static int pixis_disable_watchdog_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200287 char * const argv[])
Jon Loeliger126aa702006-05-30 17:47:00 -0500288{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500289 /* Disable the VELA sequencer and the watchdog */
290 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeliger126aa702006-05-30 17:47:00 -0500291
292 return 0;
293}
294
Jon Loeliger126aa702006-05-30 17:47:00 -0500295U_BOOT_CMD(
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200296 diswd, 1, 0, pixis_disable_watchdog_cmd,
297 "Disable watchdog timer",
298 ""
299);
Jon Loeliger126aa702006-05-30 17:47:00 -0500300
Liu Yubff188b2008-10-10 11:40:58 +0800301#ifdef CONFIG_PIXIS_SGMII_CMD
Timur Tabi2feb4af2010-03-31 17:44:13 -0500302
303/* Enable or disable SGMII mode for a TSEC
304 */
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200305static int pixis_set_sgmii(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Andy Fleming5a8a1632008-08-31 16:33:30 -0500306{
307 int which_tsec = -1;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500308 unsigned char mask;
309 unsigned char switch_mask;
Andy Fleming5a8a1632008-08-31 16:33:30 -0500310
Timur Tabi2feb4af2010-03-31 17:44:13 -0500311 if ((argc > 2) && (strcmp(argv[1], "all") != 0))
312 which_tsec = simple_strtoul(argv[1], NULL, 0);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500313
314 switch (which_tsec) {
Liu Yubff188b2008-10-10 11:40:58 +0800315#ifdef CONFIG_TSEC1
Andy Fleming5a8a1632008-08-31 16:33:30 -0500316 case 1:
317 mask = PIXIS_VSPEED2_TSEC1SER;
318 switch_mask = PIXIS_VCFGEN1_TSEC1SER;
319 break;
Liu Yubff188b2008-10-10 11:40:58 +0800320#endif
321#ifdef CONFIG_TSEC2
322 case 2:
323 mask = PIXIS_VSPEED2_TSEC2SER;
324 switch_mask = PIXIS_VCFGEN1_TSEC2SER;
325 break;
326#endif
327#ifdef CONFIG_TSEC3
Andy Fleming5a8a1632008-08-31 16:33:30 -0500328 case 3:
329 mask = PIXIS_VSPEED2_TSEC3SER;
330 switch_mask = PIXIS_VCFGEN1_TSEC3SER;
331 break;
Liu Yubff188b2008-10-10 11:40:58 +0800332#endif
333#ifdef CONFIG_TSEC4
334 case 4:
335 mask = PIXIS_VSPEED2_TSEC4SER;
336 switch_mask = PIXIS_VCFGEN1_TSEC4SER;
337 break;
338#endif
Andy Fleming5a8a1632008-08-31 16:33:30 -0500339 default:
Liu Yubff188b2008-10-10 11:40:58 +0800340 mask = PIXIS_VSPEED2_MASK;
341 switch_mask = PIXIS_VCFGEN1_MASK;
Andy Fleming5a8a1632008-08-31 16:33:30 -0500342 break;
343 }
344
345 /* Toggle whether the switches or FPGA control the settings */
346 if (!strcmp(argv[argc - 1], "switch"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500347 clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500348 else
Kumar Gala048e7ef2009-07-22 10:12:39 -0500349 setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500350
351 /* If it's not the switches, enable or disable SGMII, as specified */
352 if (!strcmp(argv[argc - 1], "on"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500353 clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500354 else if (!strcmp(argv[argc - 1], "off"))
Kumar Gala048e7ef2009-07-22 10:12:39 -0500355 setbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Fleming5a8a1632008-08-31 16:33:30 -0500356
357 return 0;
358}
359
360U_BOOT_CMD(
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200361 pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
362 "pixis_set_sgmii"
363 " - Enable or disable SGMII mode for a given TSEC \n",
364 "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
365 " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
366 " on - enables SGMII\n"
367 " off - disables SGMII\n"
368 " switch - use switch settings"
369);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500370
Andy Fleming5a8a1632008-08-31 16:33:30 -0500371#endif
372
Jon Loeliger126aa702006-05-30 17:47:00 -0500373/*
374 * This function takes the non-integral cpu:mpx pll ratio
375 * and converts it to an integer that can be used to assign
376 * FPGA register values.
377 * input: strptr i.e. argv[2]
378 */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500379static unsigned long strfractoint(char *strptr)
Jon Loeliger126aa702006-05-30 17:47:00 -0500380{
Timur Tabi2feb4af2010-03-31 17:44:13 -0500381 int i, j;
Jon Loeliger126aa702006-05-30 17:47:00 -0500382 int mulconst;
Kumar Gala8dbd4b72011-11-09 10:02:11 -0600383 int no_dec = 0;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500384 unsigned long intval = 0, decval = 0;
385 char intarr[3], decarr[3];
Jon Loeliger126aa702006-05-30 17:47:00 -0500386
387 /* Assign the integer part to intarr[]
388 * If there is no decimal point i.e.
389 * if the ratio is an integral value
390 * simply create the intarr.
391 */
392 i = 0;
James Yang16c3cde2008-01-16 11:58:08 -0600393 while (strptr[i] != '.') {
Jon Loeliger126aa702006-05-30 17:47:00 -0500394 if (strptr[i] == 0) {
395 no_dec = 1;
396 break;
397 }
398 intarr[i] = strptr[i];
399 i++;
400 }
401
Jon Loeliger126aa702006-05-30 17:47:00 -0500402 intarr[i] = '\0';
403
404 if (no_dec) {
405 /* Currently needed only for single digit corepll ratios */
Jon Loeliger80e955c2006-08-22 12:25:27 -0500406 mulconst = 10;
Jon Loeliger126aa702006-05-30 17:47:00 -0500407 decval = 0;
408 } else {
409 j = 0;
Jon Loeliger80e955c2006-08-22 12:25:27 -0500410 i++; /* Skipping the decimal point */
James Yang16c3cde2008-01-16 11:58:08 -0600411 while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
Jon Loeliger126aa702006-05-30 17:47:00 -0500412 decarr[j] = strptr[i];
413 i++;
414 j++;
415 }
416
Jon Loeliger126aa702006-05-30 17:47:00 -0500417 decarr[j] = '\0';
418
419 mulconst = 1;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500420 for (i = 0; i < j; i++)
Jon Loeliger126aa702006-05-30 17:47:00 -0500421 mulconst *= 10;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500422 decval = simple_strtoul(decarr, NULL, 10);
Jon Loeliger126aa702006-05-30 17:47:00 -0500423 }
424
Timur Tabi2feb4af2010-03-31 17:44:13 -0500425 intval = simple_strtoul(intarr, NULL, 10);
Jon Loeliger126aa702006-05-30 17:47:00 -0500426 intval = intval * mulconst;
427
Timur Tabi2feb4af2010-03-31 17:44:13 -0500428 return intval + decval;
Jon Loeliger126aa702006-05-30 17:47:00 -0500429}
Haiying Wang3d98b852007-01-22 12:37:30 -0600430
Wolfgang Denk54841ab2010-06-28 22:00:46 +0200431static int pixis_reset_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
Haiying Wang3d98b852007-01-22 12:37:30 -0600432{
James Yang16c3cde2008-01-16 11:58:08 -0600433 unsigned int i;
434 char *p_cf = NULL;
435 char *p_cf_sysclk = NULL;
436 char *p_cf_corepll = NULL;
437 char *p_cf_mpxpll = NULL;
438 char *p_altbank = NULL;
439 char *p_wd = NULL;
Timur Tabi2feb4af2010-03-31 17:44:13 -0500440 int unknown_param = 0;
Haiying Wang3d98b852007-01-22 12:37:30 -0600441
442 /*
443 * No args is a simple reset request.
444 */
445 if (argc <= 1) {
446 pixis_reset();
447 /* not reached */
448 }
449
James Yang16c3cde2008-01-16 11:58:08 -0600450 for (i = 1; i < argc; i++) {
451 if (strcmp(argv[i], "cf") == 0) {
452 p_cf = argv[i];
453 if (i + 3 >= argc) {
454 break;
Haiying Wang3d98b852007-01-22 12:37:30 -0600455 }
James Yang16c3cde2008-01-16 11:58:08 -0600456 p_cf_sysclk = argv[i+1];
457 p_cf_corepll = argv[i+2];
458 p_cf_mpxpll = argv[i+3];
459 i += 3;
460 continue;
Haiying Wang3d98b852007-01-22 12:37:30 -0600461 }
462
James Yang16c3cde2008-01-16 11:58:08 -0600463 if (strcmp(argv[i], "altbank") == 0) {
464 p_altbank = argv[i];
465 continue;
466 }
467
468 if (strcmp(argv[i], "wd") == 0) {
469 p_wd = argv[i];
470 continue;
471 }
472
473 unknown_param = 1;
474 }
475
476 /*
477 * Check that cf has all required parms
478 */
479 if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200480 || unknown_param) {
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500481#ifdef CONFIG_SYS_LONGHELP
James Yang16c3cde2008-01-16 11:58:08 -0600482 puts(cmdtp->help);
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500483#endif
Haiying Wang3d98b852007-01-22 12:37:30 -0600484 return 1;
485 }
486
James Yang16c3cde2008-01-16 11:58:08 -0600487 /*
488 * PIXIS seems to be sensitive to the ordering of
489 * the registers that are touched.
490 */
491 read_from_px_regs(0);
492
Timur Tabi2feb4af2010-03-31 17:44:13 -0500493 if (p_altbank)
James Yang16c3cde2008-01-16 11:58:08 -0600494 read_from_px_regs_altbank(0);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500495
James Yang16c3cde2008-01-16 11:58:08 -0600496 clear_altbank();
497
498 /*
499 * Clock configuration specified.
500 */
501 if (p_cf) {
502 unsigned long sysclk;
503 unsigned long corepll;
504 unsigned long mpxpll;
505
506 sysclk = simple_strtoul(p_cf_sysclk, NULL, 10);
Timur Tabi2feb4af2010-03-31 17:44:13 -0500507 corepll = strfractoint(p_cf_corepll);
James Yang16c3cde2008-01-16 11:58:08 -0600508 mpxpll = simple_strtoul(p_cf_mpxpll, NULL, 10);
509
510 if (!(set_px_sysclk(sysclk)
511 && set_px_corepll(corepll)
512 && set_px_mpxpll(mpxpll))) {
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500513#ifdef CONFIG_SYS_LONGHELP
James Yang16c3cde2008-01-16 11:58:08 -0600514 puts(cmdtp->help);
Ed Swarthoutf7fecc32008-10-08 23:38:01 -0500515#endif
James Yang16c3cde2008-01-16 11:58:08 -0600516 return 1;
517 }
518 read_from_px_regs(1);
519 }
520
521 /*
522 * Altbank specified
523 *
524 * NOTE CHANGE IN BEHAVIOR: previous code would default
525 * to enabling watchdog if altbank is specified.
526 * Now the watchdog must be enabled explicitly using 'wd'.
527 */
528 if (p_altbank) {
529 set_altbank();
530 read_from_px_regs_altbank(1);
531 }
532
533 /*
534 * Reset with watchdog specified.
535 */
Timur Tabi2feb4af2010-03-31 17:44:13 -0500536 if (p_wd)
James Yang16c3cde2008-01-16 11:58:08 -0600537 set_px_go_with_watchdog();
Timur Tabi2feb4af2010-03-31 17:44:13 -0500538 else
James Yang16c3cde2008-01-16 11:58:08 -0600539 set_px_go();
James Yang16c3cde2008-01-16 11:58:08 -0600540
541 /*
542 * Shouldn't be reached.
543 */
Haiying Wang3d98b852007-01-22 12:37:30 -0600544 return 0;
545}
546
547
548U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549 pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
Peter Tyser2fb26042009-01-27 18:03:12 -0600550 "Reset the board using the FPGA sequencer",
Haiying Wang3d98b852007-01-22 12:37:30 -0600551 " pixis_reset\n"
552 " pixis_reset [altbank]\n"
553 " pixis_reset altbank wd\n"
554 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
Wolfgang Denka89c33d2009-05-24 17:06:54 +0200555 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
556);