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gerrit.cesnet.cz / github / trini / u-boot / 9fa32b12370236a39090d4e42b013910d123db61 / . / board / muas3001 / muas3001.c
blob: e0c4dbaeba583a3cae22f9fdc93296e786c1daed [file] [log] [blame]
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]1/*
2 * (C) Copyright 2008
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <mpc8260.h>
10#include <ioports.h>
11
12#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
13#include <libfdt.h>
14#endif
15
16/*
17 * I/O Port configuration table
18 *
19 * if conf is 1, then that port pin will be configured at boot time
20 * according to the five values podr/pdir/ppar/psor/pdat for that entry
21 */
22const iop_conf_t iop_conf_tab[4][32] = {
23
24 /* Port A */
25 { /* conf ppar psor pdir podr pdat */
26 /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */
27 /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */
28 /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */
29 /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */
30 /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */
31 /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */
32 /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */
33 /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */
34 /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
35 /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
36 /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */
37 /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */
38 /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */
39 /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */
40 /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */
41 /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */
42 /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */
43 /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */
44 /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
45 /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */
46 /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
47 /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */
48 /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */
49 /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
50 /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
51 /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
52 /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
53 /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
54 /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
55 /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
56 /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
57 /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
58 },
59
60 /* Port B */
61 { /* conf ppar psor pdir podr pdat */
62 /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */
63 /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */
64 /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */
65 /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
66 /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */
67 /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */
68 /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */
69 /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */
70 /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */
71 /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */
72 /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */
73 /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */
74 /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */
75 /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */
76 /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
77 /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
78 /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
79 /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */
80 /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
81 /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
82 /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
83 /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
84 /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
85 /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */
86 /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
87 /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
88 /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
89 /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
90 /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
91 /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
92 /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
93 /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
94 },
95
96 /* Port C */
97 { /* conf ppar psor pdir podr pdat */
98 /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
99 /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */
100 /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
101 /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
102 /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
103 /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
104 /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
105 /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
106 /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
107 /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
108 /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */
109 /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */
110 /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
111 /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */
112 /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
113 /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
114 /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
115 /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
116 /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
117 /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */
118 /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */
119 /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
120 /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */
121 /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
122 /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
123 /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
124 /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
125 /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
126 /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
127 /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
128 /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
129 /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
130 },
131
132 /* Port D */
133 { /* conf ppar psor pdir podr pdat */
134 /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
135 /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
136 /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
137 /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
138 /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
139 /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
140 /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
141 /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
142 /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
143 /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */
144 /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */
145 /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
146 /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
147 /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
148 /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
149 /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
Heiko Schocher0b7c5632008-09-10 11:15:28 +0200[diff] [blame]150#if defined(CONFIG_HARD_I2C)
151 /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
152 /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
153#else
154 /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */
155 /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */
156#endif
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]157 /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
158 /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
159 /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
160 /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
161 /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
162 /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
163 /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
164 /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
165 /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
166 /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
167 /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
168 /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
169 /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
170 /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
171 }
172};
173
174/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx
175 *
176 * This routine performs standard 8260 initialization sequence
177 * and calculates the available memory size. It may be called
178 * several times to try different SDRAM configurations on both
179 * 60x and local buses.
180 */
181static long int try_init (volatile memctl8260_t * memctl, ulong sdmr,
182 ulong orx, volatile uchar * base)
183{
184 volatile uchar c = 0xff;
185 volatile uint *sdmr_ptr;
186 volatile uint *orx_ptr;
187 ulong maxsize, size;
188 int i;
189
190 /* We must be able to test a location outsize the maximum legal size
191 * to find out THAT we are outside; but this address still has to be
192 * mapped by the controller. That means, that the initial mapping has
193 * to be (at least) twice as large as the maximum expected size.
194 */
195 maxsize = (1 + (~orx | 0x7fff))/* / 2*/;
196
197 sdmr_ptr = &memctl->memc_psdmr;
198 orx_ptr = &memctl->memc_or1;
199
200 *orx_ptr = orx;
201
202 /*
203 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
204 *
205 * "At system reset, initialization software must set up the
206 * programmable parameters in the memory controller banks registers
207 * (ORx, BRx, P/LSDMR). After all memory parameters are configured,
208 * system software should execute the following initialization sequence
209 * for each SDRAM device.
210 *
211 * 1. Issue a PRECHARGE-ALL-BANKS command
212 * 2. Issue eight CBR REFRESH commands
213 * 3. Issue a MODE-SET command to initialize the mode register
214 *
215 * The initial commands are executed by setting P/LSDMR[OP] and
216 * accessing the SDRAM with a single-byte transaction."
217 *
218 * The appropriate BRx/ORx registers have already been set when we
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]219 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]220 */
221
222 *sdmr_ptr = sdmr | PSDMR_OP_PREA;
223 *base = c;
224
225 *sdmr_ptr = sdmr | PSDMR_OP_CBRR;
226 for (i = 0; i < 8; i++)
227 *base = c;
228
229 *sdmr_ptr = sdmr | PSDMR_OP_MRW;
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]230 *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]231
232 *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
233 *base = c;
234
235 size = get_ram_size ((long *)base, maxsize);
236 *orx_ptr = orx | ~(size - 1);
237
238 return (size);
239}
240
241phys_size_t initdram (int board_type)
242{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]243 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]244 volatile memctl8260_t *memctl = &immap->im_memctl;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]245 long psize;
Heiko Schochera55d0742008-09-08 10:19:36 +0200[diff] [blame]246 long sizelittle, sizebig;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]247
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]248 memctl->memc_psrt = CONFIG_SYS_PSRT;
249 memctl->memc_mptpr = CONFIG_SYS_MPTPR;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]250
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]251 /* 60x SDRAM setup:
252 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]253 sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
254 (uchar *) CONFIG_SYS_SDRAM_BASE);
255 sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
256 (uchar *) CONFIG_SYS_SDRAM_BASE);
Heiko Schochera55d0742008-09-08 10:19:36 +0200[diff] [blame]257 if (sizelittle < sizebig) {
258 psize = sizebig;
259 } else {
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]260 psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
261 (uchar *) CONFIG_SYS_SDRAM_BASE);
Heiko Schochera55d0742008-09-08 10:19:36 +0200[diff] [blame]262 }
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]263
264 icache_enable ();
265
266 return (psize);
267}
268
269int checkboard (void)
270{
271 puts ("Board: MUAS3001\n");
272
273 return 0;
274}
275
276/*
277 * Early board initalization.
278 */
279int board_early_init_r (void)
280{
281 return 0;
282}
283
284#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
Masahiro Yamada8e261572014-04-04 20:09:58 +0900[diff] [blame]285DECLARE_GLOBAL_DATA_PTR;
286
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]287/*
288 * update "memory" property in the blob
289 */
290void ft_blob_update (void *blob, bd_t *bd)
291{
292 int ret, nodeoffset = 0;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]293 ulong flash_data[4] = {0};
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]294 ulong speed = 0;
295
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]296 /* update Flash addr, size */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]297 flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
298 flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]299 nodeoffset = fdt_path_offset (blob, "/localbus");
300 if (nodeoffset >= 0) {
301 ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
302 sizeof (flash_data));
303 if (ret < 0)
304 printf ("ft_blob_update): cannot set /localbus/ranges "
305 "property err:%s\n", fdt_strerror(ret));
306 } else {
307 /* memory node is required in dts */
308 printf ("ft_blob_update(): cannot find /localbus node "
309 "err:%s\n", fdt_strerror (nodeoffset));
310 }
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]311
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]312 /* baudrate */
313 nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial");
314 if (nodeoffset >= 0) {
Masahiro Yamada8e261572014-04-04 20:09:58 +0900[diff] [blame]315 speed = cpu_to_be32 (gd->baudrate);
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]316 ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed,
317 sizeof (unsigned long));
318 if (ret < 0)
319 printf ("ft_blob_update): cannot set /soc/cpm/serial/current-speed "
320 "property err:%s\n", fdt_strerror (ret));
321 } else {
322 /* baudrate is required in dts */
323 printf ("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node "
324 "err:%s\n", fdt_strerror (nodeoffset));
325 }
326}
327
Simon Glasse895a4b2014-10-23 18:58:47 -0600[diff] [blame]328int ft_board_setup(void *blob, bd_t *bd)
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]329{
330 ft_cpu_setup (blob, bd);
331 ft_blob_update (blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600[diff] [blame]332
333 return 0;
Heiko Schocheradf22b62008-08-19 10:08:49 +0200[diff] [blame]334}
335#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */