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Nobuhiro Iwamatsu1d0e9272013-11-21 17:06:45 +09001/*
2 * arch/arm/include/asm/arch-rmobile/r8a7790.h
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * SPDX-License-Identifier: GPL-2.0
7 */
8
9#ifndef __ASM_ARCH_R8A7790_H
10#define __ASM_ARCH_R8A7790_H
11
12/*
13 * R8A7790 I/O Addresses
14 */
15#define RWDT_BASE 0xE6020000
16#define SWDT_BASE 0xE6030000
17#define LBSC_BASE 0xFEC00200
18#define DBSC3_0_BASE 0xE6790000
19#define DBSC3_1_BASE 0xE67A0000
20#define TMU_BASE 0xE61E0000
21#define GPIO5_BASE 0xE6055000
Nobuhiro Iwamatsu82852762014-01-08 10:14:26 +090022#define SH_QSPI_BASE 0xE6B10000
Nobuhiro Iwamatsu1d0e9272013-11-21 17:06:45 +090023
24#define S3C_BASE 0xE6784000
25#define S3C_INT_BASE 0xE6784A00
26#define S3C_MEDIA_BASE 0xE6784B00
27
28#define S3C_QOS_DCACHE_BASE 0xE6784BDC
29#define S3C_QOS_CCI0_BASE 0xE6784C00
30#define S3C_QOS_CCI1_BASE 0xE6784C24
31#define S3C_QOS_MXI_BASE 0xE6784C48
32#define S3C_QOS_AXI_BASE 0xE6784C6C
33
34#define DBSC3_0_QOS_R0_BASE 0xE6791000
35#define DBSC3_0_QOS_R1_BASE 0xE6791100
36#define DBSC3_0_QOS_R2_BASE 0xE6791200
37#define DBSC3_0_QOS_R3_BASE 0xE6791300
38#define DBSC3_0_QOS_R4_BASE 0xE6791400
39#define DBSC3_0_QOS_R5_BASE 0xE6791500
40#define DBSC3_0_QOS_R6_BASE 0xE6791600
41#define DBSC3_0_QOS_R7_BASE 0xE6791700
42#define DBSC3_0_QOS_R8_BASE 0xE6791800
43#define DBSC3_0_QOS_R9_BASE 0xE6791900
44#define DBSC3_0_QOS_R10_BASE 0xE6791A00
45#define DBSC3_0_QOS_R11_BASE 0xE6791B00
46#define DBSC3_0_QOS_R12_BASE 0xE6791C00
47#define DBSC3_0_QOS_R13_BASE 0xE6791D00
48#define DBSC3_0_QOS_R14_BASE 0xE6791E00
49#define DBSC3_0_QOS_R15_BASE 0xE6791F00
50#define DBSC3_0_QOS_W0_BASE 0xE6792000
51#define DBSC3_0_QOS_W1_BASE 0xE6792100
52#define DBSC3_0_QOS_W2_BASE 0xE6792200
53#define DBSC3_0_QOS_W3_BASE 0xE6792300
54#define DBSC3_0_QOS_W4_BASE 0xE6792400
55#define DBSC3_0_QOS_W5_BASE 0xE6792500
56#define DBSC3_0_QOS_W6_BASE 0xE6792600
57#define DBSC3_0_QOS_W7_BASE 0xE6792700
58#define DBSC3_0_QOS_W8_BASE 0xE6792800
59#define DBSC3_0_QOS_W9_BASE 0xE6792900
60#define DBSC3_0_QOS_W10_BASE 0xE6792A00
61#define DBSC3_0_QOS_W11_BASE 0xE6792B00
62#define DBSC3_0_QOS_W12_BASE 0xE6792C00
63#define DBSC3_0_QOS_W13_BASE 0xE6792D00
64#define DBSC3_0_QOS_W14_BASE 0xE6792E00
65#define DBSC3_0_QOS_W15_BASE 0xE6792F00
66
67#define DBSC3_0_DBADJ2 0xE67900C8
68
69#define CCI_400_MAXOT_1 0xF0091110
70#define CCI_400_MAXOT_2 0xF0092110
71#define CCI_400_QOSCNTL_1 0xF009110C
72#define CCI_400_QOSCNTL_2 0xF009210C
73
74#define MXI_BASE 0xFE960000
75#define MXI_QOS_BASE 0xFE960300
76
77#define SYS_AXI_SYX64TO128_BASE 0xFF800300
78#define SYS_AXI_AVB_BASE 0xFF800340
79#define SYS_AXI_G2D_BASE 0xFF800540
80#define SYS_AXI_IMP0_BASE 0xFF800580
81#define SYS_AXI_IMP1_BASE 0xFF8005C0
82#define SYS_AXI_IMUX0_BASE 0xFF800600
83#define SYS_AXI_IMUX1_BASE 0xFF800640
84#define SYS_AXI_IMUX2_BASE 0xFF800680
85#define SYS_AXI_LBS_BASE 0xFF8006C0
86#define SYS_AXI_MMUDS_BASE 0xFF800700
87#define SYS_AXI_MMUM_BASE 0xFF800740
88#define SYS_AXI_MMUR_BASE 0xFF800780
89#define SYS_AXI_MMUS0_BASE 0xFF8007C0
90#define SYS_AXI_MMUS1_BASE 0xFF800800
91#define SYS_AXI_MTSB0_BASE 0xFF800880
92#define SYS_AXI_MTSB1_BASE 0xFF8008C0
93#define SYS_AXI_PCI_BASE 0xFF800900
94#define SYS_AXI_RTX_BASE 0xFF800940
95#define SYS_AXI_SDS0_BASE 0xFF800A80
96#define SYS_AXI_SDS1_BASE 0xFF800AC0
97#define SYS_AXI_USB20_BASE 0xFF800C00
98#define SYS_AXI_USB21_BASE 0xFF800C40
99#define SYS_AXI_USB22_BASE 0xFF800C80
100#define SYS_AXI_USB30_BASE 0xFF800CC0
101
102#define RT_AXI_SHX_BASE 0xFF810100
103#define RT_AXI_RDS_BASE 0xFF8101C0
104#define RT_AXI_RTX64TO128_BASE 0xFF810200
105#define RT_AXI_STPRO_BASE 0xFF810240
106
107#define MP_AXI_ADSP_BASE 0xFF820100
108#define MP_AXI_ASDS0_BASE 0xFF8201C0
109#define MP_AXI_ASDS1_BASE 0xFF820200
110#define MP_AXI_MLP_BASE 0xFF820240
111#define MP_AXI_MMUMP_BASE 0xFF820280
112#define MP_AXI_SPU_BASE 0xFF8202C0
113#define MP_AXI_SPUC_BASE 0xFF820300
114
115#define SYS_AXI256_AXI128TO256_BASE 0xFF860100
116#define SYS_AXI256_SYX_BASE 0xFF860140
117#define SYS_AXI256_MPX_BASE 0xFF860180
118#define SYS_AXI256_MXI_BASE 0xFF8601C0
119
120#define CCI_AXI_MMUS0_BASE 0xFF880100
121#define CCI_AXI_SYX2_BASE 0xFF880140
122#define CCI_AXI_MMUR_BASE 0xFF880180
123#define CCI_AXI_MMUDS_BASE 0xFF8801C0
124#define CCI_AXI_MMUM_BASE 0xFF880200
125#define CCI_AXI_MXI_BASE 0xFF880240
126#define CCI_AXI_MMUS1_BASE 0xFF880280
127#define CCI_AXI_MMUMP_BASE 0xFF8802C0
128
129#define MEDIA_AXI_JPR_BASE 0xFE964100
130#define MEDIA_AXI_JPW_BASE 0xFE966100
131#define MEDIA_AXI_GCU0R_BASE 0xFE964140
132#define MEDIA_AXI_GCU0W_BASE 0xFE966140
133#define MEDIA_AXI_GCU1R_BASE 0xFE964180
134#define MEDIA_AXI_GCU1W_BASE 0xFE966180
135#define MEDIA_AXI_TDMR_BASE 0xFE964500
136#define MEDIA_AXI_TDMW_BASE 0xFE966500
137#define MEDIA_AXI_VSP0CR_BASE 0xFE964540
138#define MEDIA_AXI_VSP0CW_BASE 0xFE966540
139#define MEDIA_AXI_VSP1CR_BASE 0xFE964580
140#define MEDIA_AXI_VSP1CW_BASE 0xFE966580
141#define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
142#define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
143#define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
144#define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
145#define MEDIA_AXI_VIN0W_BASE 0xFE966900
146#define MEDIA_AXI_VSP0R_BASE 0xFE964D00
147#define MEDIA_AXI_VSP0W_BASE 0xFE966D00
148#define MEDIA_AXI_FDP0R_BASE 0xFE964D40
149#define MEDIA_AXI_FDP0W_BASE 0xFE966D40
150#define MEDIA_AXI_IMSR_BASE 0xFE964D80
151#define MEDIA_AXI_IMSW_BASE 0xFE966D80
152#define MEDIA_AXI_VSP1R_BASE 0xFE965100
153#define MEDIA_AXI_VSP1W_BASE 0xFE967100
154#define MEDIA_AXI_FDP1R_BASE 0xFE965140
155#define MEDIA_AXI_FDP1W_BASE 0xFE967140
156#define MEDIA_AXI_IMRR_BASE 0xFE965180
157#define MEDIA_AXI_IMRW_BASE 0xFE967180
158#define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
159#define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
160#define MEDIA_AXI_VSPD0R_BASE 0xFE965500
161#define MEDIA_AXI_VSPD0W_BASE 0xFE967500
162#define MEDIA_AXI_VSPD1R_BASE 0xFE965540
163#define MEDIA_AXI_VSPD1W_BASE 0xFE967540
164#define MEDIA_AXI_DU0R_BASE 0xFE965580
165#define MEDIA_AXI_DU0W_BASE 0xFE967580
166#define MEDIA_AXI_DU1R_BASE 0xFE9655C0
167#define MEDIA_AXI_DU1W_BASE 0xFE9675C0
168#define MEDIA_AXI_VCP0CR_BASE 0xFE965900
169#define MEDIA_AXI_VCP0CW_BASE 0xFE967900
170#define MEDIA_AXI_VCP0VR_BASE 0xFE965940
171#define MEDIA_AXI_VCP0VW_BASE 0xFE967940
172#define MEDIA_AXI_VPC0R_BASE 0xFE965980
173#define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
174#define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
175#define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
176#define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
177#define MEDIA_AXI_VPC1R_BASE 0xFE965D80
178
179#define SYS_AXI_AVBDMSCR 0xFF802000
180#define SYS_AXI_SYX2DMSCR 0xFF802004
181#define SYS_AXI_CC50DMSCR 0xFF802008
182#define SYS_AXI_CC51DMSCR 0xFF80200C
183#define SYS_AXI_CCIDMSCR 0xFF802010
184#define SYS_AXI_CSDMSCR 0xFF802014
185#define SYS_AXI_DDMDMSCR 0xFF802018
186#define SYS_AXI_ETHDMSCR 0xFF80201C
187#define SYS_AXI_G2DDMSCR 0xFF802020
188#define SYS_AXI_IMP0DMSCR 0xFF802024
189#define SYS_AXI_IMP1DMSCR 0xFF802028
190#define SYS_AXI_LBSDMSCR 0xFF80202C
191#define SYS_AXI_MMUDSDMSCR 0xFF802030
192#define SYS_AXI_MMUMXDMSCR 0xFF802034
193#define SYS_AXI_MMURDDMSCR 0xFF802038
194#define SYS_AXI_MMUS0DMSCR 0xFF80203C
195#define SYS_AXI_MMUS1DMSCR 0xFF802040
196#define SYS_AXI_MPXDMSCR 0xFF802044
197#define SYS_AXI_MTSB0DMSCR 0xFF802048
198#define SYS_AXI_MTSB1DMSCR 0xFF80204C
199#define SYS_AXI_PCIDMSCR 0xFF802050
200#define SYS_AXI_RTXDMSCR 0xFF802054
201#define SYS_AXI_SAT0DMSCR 0xFF802058
202#define SYS_AXI_SAT1DMSCR 0xFF80205C
203#define SYS_AXI_SDM0DMSCR 0xFF802060
204#define SYS_AXI_SDM1DMSCR 0xFF802064
205#define SYS_AXI_SDS0DMSCR 0xFF802068
206#define SYS_AXI_SDS1DMSCR 0xFF80206C
207#define SYS_AXI_ETRABDMSCR 0xFF802070
208#define SYS_AXI_ETRKFDMSCR 0xFF802074
209#define SYS_AXI_UDM0DMSCR 0xFF802078
210#define SYS_AXI_UDM1DMSCR 0xFF80207C
211#define SYS_AXI_USB20DMSCR 0xFF802080
212#define SYS_AXI_USB21DMSCR 0xFF802084
213#define SYS_AXI_USB22DMSCR 0xFF802088
214#define SYS_AXI_USB30DMSCR 0xFF80208C
215#define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
216#define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
217#define SYS_AXI_AVBSLVDMSCR 0xFF802108
218#define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
219#define SYS_AXI_ETHSLVDMSCR 0xFF802110
220#define SYS_AXI_GICSLVDMSCR 0xFF802114
221#define SYS_AXI_IMPSLVDMSCR 0xFF802118
222#define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
223#define SYS_AXI_IMX1SLVDMSCR 0xFF802120
224#define SYS_AXI_IMX2SLVDMSCR 0xFF802124
225#define SYS_AXI_LBSSLVDMSCR 0xFF802128
226#define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
227#define SYS_AXI_MMC1SLVDMSCR 0xFF802130
228#define SYS_AXI_MPXSLVDMSCR 0xFF802134
229#define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
230#define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
231#define SYS_AXI_MXTSLVDMSCR 0xFF802140
232#define SYS_AXI_PCISLVDMSCR 0xFF802144
233#define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
234#define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
235#define SYS_AXI_RTXSLVDMSCR 0xFF802150
236#define SYS_AXI_SAT0SLVDMSCR 0xFF802168
237#define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
238#define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
239#define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
240#define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
241#define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
242#define SYS_AXI_SGXSLVDMSCR 0xFF802180
243#define SYS_AXI_STBSLVDMSCR 0xFF802188
244#define SYS_AXI_STMSLVDMSCR 0xFF80218C
245#define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
246#define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
247#define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
248#define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
249#define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
250#define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
251#define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
252
253#define RT_AXI_CBMDMSCR 0xFF812000
254#define RT_AXI_DBDMSCR 0xFF812004
255#define RT_AXI_RDMDMSCR 0xFF812008
256#define RT_AXI_RDSDMSCR 0xFF81200C
257#define RT_AXI_STRDMSCR 0xFF812010
258#define RT_AXI_SY2RTDMSCR 0xFF812014
259#define RT_AXI_CBSSLVDMSCR 0xFF812100
260#define RT_AXI_DBSSLVDMSCR 0xFF812104
261#define RT_AXI_RTAP1SLVDMSCR 0xFF812108
262#define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
263#define RT_AXI_RTAP3SLVDMSCR 0xFF812110
264#define RT_AXI_RT2SYSLVDMSCR 0xFF812114
265#define RT_AXI_A128TO64SLVDMSCR 0xFF812118
266#define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
267#define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
268#define RT_AXI_UTLBRSLVDMSCR 0xFF812128
269
270#define MP_AXI_ADSPDMSCR 0xFF822000
271#define MP_AXI_ASDM0DMSCR 0xFF822004
272#define MP_AXI_ASDM1DMSCR 0xFF822008
273#define MP_AXI_ASDS0DMSCR 0xFF82200C
274#define MP_AXI_ASDS1DMSCR 0xFF822010
275#define MP_AXI_MLPDMSCR 0xFF822014
276#define MP_AXI_MMUMPDMSCR 0xFF822018
277#define MP_AXI_SPUDMSCR 0xFF82201C
278#define MP_AXI_SPUCDMSCR 0xFF822020
279#define MP_AXI_SY2MPDMSCR 0xFF822024
280#define MP_AXI_ADSPSLVDMSCR 0xFF822100
281#define MP_AXI_MLMSLVDMSCR 0xFF822104
282#define MP_AXI_MPAP4SLVDMSCR 0xFF822108
283#define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
284#define MP_AXI_MPAP6SLVDMSCR 0xFF822110
285#define MP_AXI_MPAP7SLVDMSCR 0xFF822114
286#define MP_AXI_MP2SYSLVDMSCR 0xFF822118
287#define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
288#define MP_AXI_MPXAPSLVDMSCR 0xFF822124
289#define MP_AXI_SPUSLVDMSCR 0xFF822128
290#define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
291
292#define ADM_AXI_ASDM0DMSCR 0xFF842000
293#define ADM_AXI_ASDM1DMSCR 0xFF842004
294#define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
295#define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
296#define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
297
298#define DM_AXI_RDMDMSCR 0xFF852000
299#define DM_AXI_SDM0DMSCR 0xFF852004
300#define DM_AXI_SDM1DMSCR 0xFF852008
301#define DM_AXI_MMAP0SLVDMSCR 0xFF852100
302#define DM_AXI_MMAP1SLVDMSCR 0xFF852104
303#define DM_AXI_QSPAPSLVDMSCR 0xFF852108
304#define DM_AXI_RAP4SLVDMSCR 0xFF85210C
305#define DM_AXI_RAP5SLVDMSCR 0xFF852110
306#define DM_AXI_SAP4SLVDMSCR 0xFF852114
307#define DM_AXI_SAP5SLVDMSCR 0xFF852118
308#define DM_AXI_SAP6SLVDMSCR 0xFF85211C
309#define DM_AXI_SAP65SLVDMSCR 0xFF852120
310#define DM_AXI_SDAP0SLVDMSCR 0xFF852124
311#define DM_AXI_SDAP1SLVDMSCR 0xFF852128
312#define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
313#define DM_AXI_SDAP3SLVDMSCR 0xFF852130
314
315#define SYS_AXI256_SYXDMSCR 0xFF862000
316#define SYS_AXI256_MPXDMSCR 0xFF862004
317#define SYS_AXI256_MXIDMSCR 0xFF862008
318#define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
319#define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
320#define SYS_AXI256_SYXSLVDMSCR 0xFF862108
321#define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
322#define SYS_AXI256_S3CSLVDMSCR 0xFF862110
323
324#define MXT_SYXDMSCR 0xFF872000
325#define MXT_CMM0SLVDMSCR 0xFF872100
326#define MXT_CMM1SLVDMSCR 0xFF872104
327#define MXT_CMM2SLVDMSCR 0xFF872108
328#define MXT_FDPSLVDMSCR 0xFF87210C
329#define MXT_IMRSLVDMSCR 0xFF872110
330#define MXT_VINSLVDMSCR 0xFF872114
331#define MXT_VPC0SLVDMSCR 0xFF872118
332#define MXT_VPC1SLVDMSCR 0xFF87211C
333#define MXT_VSP0SLVDMSCR 0xFF872120
334#define MXT_VSP1SLVDMSCR 0xFF872124
335#define MXT_VSPD0SLVDMSCR 0xFF872128
336#define MXT_VSPD1SLVDMSCR 0xFF87212C
337#define MXT_MAP1SLVDMSCR 0xFF872130
338#define MXT_MAP2SLVDMSCR 0xFF872134
339
340#define CCI_AXI_MMUS0DMSCR 0xFF882000
341#define CCI_AXI_SYX2DMSCR 0xFF882004
342#define CCI_AXI_MMURDMSCR 0xFF882008
343#define CCI_AXI_MMUDSDMSCR 0xFF88200C
344#define CCI_AXI_MMUMDMSCR 0xFF882010
345#define CCI_AXI_MXIDMSCR 0xFF882014
346#define CCI_AXI_MMUS1DMSCR 0xFF882018
347#define CCI_AXI_MMUMPDMSCR 0xFF88201C
348#define CCI_AXI_DVMDMSCR 0xFF882020
349#define CCI_AXI_CCISLVDMSCR 0xFF882100
350
351#define CCI_AXI_IPMMUIDVMCR 0xFF880400
352#define CCI_AXI_IPMMURDVMCR 0xFF880404
353#define CCI_AXI_IPMMUS0DVMCR 0xFF880408
354#define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
355#define CCI_AXI_IPMMUMPDVMCR 0xFF880410
356#define CCI_AXI_IPMMUDSDVMCR 0xFF880414
357#define CCI_AXI_AX2ADDRMASK 0xFF88041C
358
359#ifndef __ASSEMBLY__
360#include <asm/types.h>
361
362/* RWDT */
363struct r8a7790_rwdt {
364 u32 rwtcnt; /* 0x00 */
365 u32 rwtcsra; /* 0x04 */
366 u16 rwtcsrb; /* 0x08 */
367};
368
369/* SWDT */
370struct r8a7790_swdt {
371 u32 swtcnt; /* 0x00 */
372 u32 swtcsra; /* 0x04 */
373 u16 swtcsrb; /* 0x08 */
374};
375
376/* LBSC */
377struct r8a7790_lbsc {
378 u32 cs0ctrl;
379 u32 cs1ctrl;
380 u32 ecs0ctrl;
381 u32 ecs1ctrl;
382 u32 ecs2ctrl;
383 u32 ecs3ctrl;
384 u32 ecs4ctrl;
385 u32 ecs5ctrl;
386 u32 dummy0[4]; /* 0x20 .. 0x2C */
387 u32 cswcr0;
388 u32 cswcr1;
389 u32 ecswcr0;
390 u32 ecswcr1;
391 u32 ecswcr2;
392 u32 ecswcr3;
393 u32 ecswcr4;
394 u32 ecswcr5;
395 u32 exdmawcr0;
396 u32 exdmawcr1;
397 u32 exdmawcr2;
398 u32 dummy1[9]; /* 0x5C .. 0x7C */
399 u32 cspwcr0;
400 u32 cspwcr1;
401 u32 ecspwcr0;
402 u32 ecspwcr1;
403 u32 ecspwcr2;
404 u32 ecspwcr3;
405 u32 ecspwcr4;
406 u32 ecspwcr5;
407 u32 exwtsync;
408 u32 dummy2[3]; /* 0xA4 .. 0xAC */
409 u32 cs0bstctl;
410 u32 cs0btph;
411 u32 dummy3[2]; /* 0xB8 .. 0xBC */
412 u32 cs1gdst;
413 u32 ecs0gdst;
414 u32 ecs1gdst;
415 u32 ecs2gdst;
416 u32 ecs3gdst;
417 u32 ecs4gdst;
418 u32 ecs5gdst;
419 u32 dummy4[5]; /* 0xDC .. 0xEC */
420 u32 exdmaset0;
421 u32 exdmaset1;
422 u32 exdmaset2;
423 u32 dummy5[5]; /* 0xFC .. 0x10C */
424 u32 exdmcr0;
425 u32 exdmcr1;
426 u32 exdmcr2;
427 u32 dummy6[5]; /* 0x11C .. 0x12C */
428 u32 bcintsr;
429 u32 bcintcr;
430 u32 bcintmr;
431 u32 dummy7; /* 0x13C */
432 u32 exbatlv;
433 u32 exwtsts;
434 u32 dummy8[14]; /* 0x148 .. 0x17C */
435 u32 atacsctrl;
436 u32 dummy9[15]; /* 0x184 .. 0x1BC */
437 u32 exbct;
438 u32 extct;
439};
440
441/* DBSC3 */
442struct r8a7790_dbsc3 {
443 u32 dummy0[3]; /* 0x00 .. 0x08 */
444 u32 dbstate1;
445 u32 dbacen;
446 u32 dbrfen;
447 u32 dbcmd;
448 u32 dbwait;
449 u32 dbkind;
450 u32 dbconf0;
451 u32 dummy1[2]; /* 0x28 .. 0x2C */
452 u32 dbphytype;
453 u32 dummy2[3]; /* 0x34 .. 0x3C */
454 u32 dbtr0;
455 u32 dbtr1;
456 u32 dbtr2;
457 u32 dummy3; /* 0x4C */
458 u32 dbtr3;
459 u32 dbtr4;
460 u32 dbtr5;
461 u32 dbtr6;
462 u32 dbtr7;
463 u32 dbtr8;
464 u32 dbtr9;
465 u32 dbtr10;
466 u32 dbtr11;
467 u32 dbtr12;
468 u32 dbtr13;
469 u32 dbtr14;
470 u32 dbtr15;
471 u32 dbtr16;
472 u32 dbtr17;
473 u32 dbtr18;
474 u32 dbtr19;
475 u32 dummy4[7]; /* 0x94 .. 0xAC */
476 u32 dbbl;
477 u32 dummy5[3]; /* 0xB4 .. 0xBC */
478 u32 dbadj0;
479 u32 dummy6; /* 0xC4 */
480 u32 dbadj2;
481 u32 dummy7[5]; /* 0xCC .. 0xDC */
482 u32 dbrfcnf0;
483 u32 dbrfcnf1;
484 u32 dbrfcnf2;
485 u32 dummy8[2]; /* 0xEC .. 0xF0 */
486 u32 dbcalcnf;
487 u32 dbcaltr;
488 u32 dummy9; /* 0xFC */
489 u32 dbrnk0;
490 u32 dummy10[31]; /* 0x104 .. 0x17C */
491 u32 dbpdncnf;
492 u32 dummy11[47]; /* 0x184 ..0x23C */
493 u32 dbdfistat;
494 u32 dbdficnt;
495 u32 dummy12[14]; /* 0x248 .. 0x27C */
496 u32 dbpdlck;
497 u32 dummy13[3]; /* 0x284 .. 0x28C */
498 u32 dbpdrga;
499 u32 dummy14[3]; /* 0x294 .. 0x29C */
500 u32 dbpdrgd;
501 u32 dummy15[24]; /* 0x2A4 .. 0x300 */
502 u32 dbbs0cnt1;
503 u32 dummy16[30]; /* 0x308 .. 0x37C */
504 u32 dbwt0cnf0;
505 u32 dbwt0cnf1;
506 u32 dbwt0cnf2;
507 u32 dbwt0cnf3;
508 u32 dbwt0cnf4;
509};
510
511/* GPIO */
512struct r8a7790_gpio {
513 u32 iointsel;
514 u32 inoutsel;
515 u32 outdt;
516 u32 indt;
517 u32 intdt;
518 u32 intclr;
519 u32 intmsk;
520 u32 posneg;
521 u32 edglevel;
522 u32 filonoff;
523 u32 intmsks;
524 u32 mskclrs;
525 u32 outdtsel;
526 u32 outdth;
527 u32 outdtl;
528 u32 bothedge;
529};
530
531/* S3C(QoS) */
532struct r8a7790_s3c {
533 u32 s3cexcladdmsk;
534 u32 s3cexclidmsk;
535 u32 s3cadsplcr;
536 u32 s3cmaar;
537 u32 s3carcr11;
538 u32 s3crorr;
539 u32 s3cworr;
540 u32 s3carcr22;
541 u32 dummy1[2]; /* 0x20 .. 0x24 */
542 u32 s3cmctr;
543 u32 dummy2; /* 0x2C */
544 u32 cconf0;
545 u32 cconf1;
546 u32 cconf2;
547 u32 cconf3;
548};
549
550struct r8a7790_s3c_qos {
551 u32 s3cqos0;
552 u32 s3cqos1;
553 u32 s3cqos2;
554 u32 s3cqos3;
555 u32 s3cqos4;
556 u32 s3cqos5;
557 u32 s3cqos6;
558 u32 s3cqos7;
559 u32 s3cqos8;
560};
561
562/* DBSC(QoS) */
563struct r8a7790_dbsc3_qos {
564 u32 dblgcnt;
565 u32 dbtmval0;
566 u32 dbtmval1;
567 u32 dbtmval2;
568 u32 dbtmval3;
569 u32 dbrqctr;
570 u32 dbthres0;
571 u32 dbthres1;
572 u32 dbthres2;
573 u32 dummy0; /* 0x24 */
574 u32 dblgqon;
575};
576
577/* MXI(QoS) */
578struct r8a7790_mxi {
579 u32 mxsaar0;
580 u32 mxsaar1;
581 u32 dummy0[7]; /* 0x08 .. 0x20 */
582 u32 mxaxiracr;
583 u32 mxs3cracr;
584 u32 dummy1[2]; /* 0x2C .. 0x30 */
585 u32 mxaxiwacr;
586 u32 mxs3cwacr;
587 u32 dummy2; /* 0x3C */
588 u32 mxrtcr;
589 u32 mxwtcr;
590};
591
592struct r8a7790_mxi_qos {
593 u32 vspdu0;
594 u32 vspdu1;
595 u32 du0;
596 u32 du1;
597};
598
599/* AXI(QoS) */
600struct r8a7790_axi_qos {
601 u32 qosconf;
602 u32 qosctset0;
603 u32 qosctset1;
604 u32 qosctset2;
605 u32 qosctset3;
606 u32 qosreqctr;
607 u32 qosthres0;
608 u32 qosthres1;
609 u32 qosthres2;
610 u32 qosqon;
611};
612
613#endif
614
615#endif /* __ASM_ARCH_R8A7790_H */