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gerrit.cesnet.cz / github / trini / u-boot / 9f2ec3f5431281a480c89107cb952ca5571d78e7 / . / board / Marvell / dreamplug / dreamplug.c
blob: b53c81080d10985faeb02992fa62f9f35864d64f [file] [log] [blame]
Jason Cooper2e0c1c72011-10-03 13:49:53 +0530[diff] [blame]1/*
2 * (C) Copyright 2011
3 * Jason Cooper <u-boot@lakedaemon.net>
4 *
5 * Based on work by:
6 * Marvell Semiconductor <www.marvell.com>
7 * Written-by: Siddarth Gore <gores@marvell.com>
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +0200[diff] [blame]9 * SPDX-License-Identifier: GPL-2.0+
Jason Cooper2e0c1c72011-10-03 13:49:53 +0530[diff] [blame]10 */
11
12#include <common.h>
13#include <miiphy.h>
Anatolij Gustschin0ac16bf2011-10-29 11:19:47 +0000[diff] [blame]14#include <asm/arch/cpu.h>
Jason Cooper2e0c1c72011-10-03 13:49:53 +0530[diff] [blame]15#include <asm/arch/kirkwood.h>
16#include <asm/arch/mpp.h>
17#include "dreamplug.h"
18
19DECLARE_GLOBAL_DATA_PTR;
20
21int board_early_init_f(void)
22{
23 /*
24 * default gpio configuration
25 * There are maximum 64 gpios controlled through 2 sets of registers
26 * the below configuration configures mainly initial LED status
27 */
28 kw_config_gpio(DREAMPLUG_OE_VAL_LOW,
29 DREAMPLUG_OE_VAL_HIGH,
30 DREAMPLUG_OE_LOW, DREAMPLUG_OE_HIGH);
31
32 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD9d86f0c2012-11-26 11:27:36 +0000[diff] [blame]33 static const u32 kwmpp_config[] = {
Jason Cooper2e0c1c72011-10-03 13:49:53 +0530[diff] [blame]34 MPP0_SPI_SCn, /* SPI Flash */
35 MPP1_SPI_MOSI,
36 MPP2_SPI_SCK,
37 MPP3_SPI_MISO,
38 MPP4_NF_IO6,
39 MPP5_NF_IO7,
40 MPP6_SYSRST_OUTn,
41 MPP7_GPO,
42 MPP8_TW_SDA,
43 MPP9_TW_SCK,
44 MPP10_UART0_TXD, /* Serial */
45 MPP11_UART0_RXD,
46 MPP12_SD_CLK, /* SDIO Slot */
47 MPP13_SD_CMD,
48 MPP14_SD_D0,
49 MPP15_SD_D1,
50 MPP16_SD_D2,
51 MPP17_SD_D3,
52 MPP18_NF_IO0,
53 MPP19_NF_IO1,
54 MPP20_GE1_0, /* Gigabit Ethernet */
55 MPP21_GE1_1,
56 MPP22_GE1_2,
57 MPP23_GE1_3,
58 MPP24_GE1_4,
59 MPP25_GE1_5,
60 MPP26_GE1_6,
61 MPP27_GE1_7,
62 MPP28_GE1_8,
63 MPP29_GE1_9,
64 MPP30_GE1_10,
65 MPP31_GE1_11,
66 MPP32_GE1_12,
67 MPP33_GE1_13,
68 MPP34_GE1_14,
69 MPP35_GE1_15,
70 MPP36_GPIO, /* 7 external GPIO pins (36 - 45) */
71 MPP37_GPIO,
72 MPP38_GPIO,
73 MPP39_GPIO,
74 MPP40_TDM_SPI_SCK,
75 MPP41_TDM_SPI_MISO,
76 MPP42_TDM_SPI_MOSI,
77 MPP43_GPIO,
78 MPP44_GPIO,
79 MPP45_GPIO,
80 MPP46_GPIO,
81 MPP47_GPIO, /* Bluetooth LED */
82 MPP48_GPIO, /* Wifi LED */
83 MPP49_GPIO, /* Wifi AP LED */
84 0
85 };
Valentin Longchamp84683632012-06-01 01:31:00 +0000[diff] [blame]86 kirkwood_mpp_conf(kwmpp_config, NULL);
Jason Cooper2e0c1c72011-10-03 13:49:53 +0530[diff] [blame]87 return 0;
88}
89
90int board_init(void)
91{
92 /* adress of boot parameters */
93 gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
94
95 return 0;
96}
97
98#ifdef CONFIG_RESET_PHY_R
99void mv_phy_88e1116_init(char *name)
100{
101 u16 reg;
102 u16 devadr;
103
104 if (miiphy_set_current_dev(name))
105 return;
106
107 /* command to read PHY dev address */
108 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
109 printf("Err..%s could not read PHY dev address\n",
110 __func__);
111 return;
112 }
113
114 /*
115 * Enable RGMII delay on Tx and Rx for CPU port
116 * Ref: sec 4.7.2 of chip datasheet
117 */
118 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
119 miiphy_read(name, devadr, MV88E1116_MAC_CTRL2_REG, &reg);
120 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
121 miiphy_write(name, devadr, MV88E1116_MAC_CTRL2_REG, reg);
122 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
123
124 /* reset the phy */
125 miiphy_reset(name, devadr);
126
127 printf("88E1116 Initialized on %s\n", name);
128}
129
130void reset_phy(void)
131{
132 /* configure and initialize both PHY's */
133 mv_phy_88e1116_init("egiga0");
134 mv_phy_88e1116_init("egiga1");
135}
136#endif /* CONFIG_RESET_PHY_R */