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Stefan Roese16c0cc12007-03-21 13:39:57 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese16c0cc12007-03-21 13:39:57 +01006 */
7
8/************************************************************************
9 * acadia.h - configuration for AMCC Acadia (405EZ)
10 ***********************************************************************/
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*-----------------------------------------------------------------------
16 * High Level Configuration Options
17 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +010018#define CONFIG_ACADIA 1 /* Board is Acadia */
Stefan Roese3cb86f32007-03-24 15:45:34 +010019#define CONFIG_405EZ 1 /* Specifc 405EZ support*/
Stefan Roese490f2042008-06-06 15:55:03 +020020
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#ifndef CONFIG_SYS_TEXT_BASE
22#define CONFIG_SYS_TEXT_BASE 0xFFF80000
23#endif
24
Stefan Roese490f2042008-06-06 15:55:03 +020025/*
26 * Include common defines/options for all AMCC eval boards
27 */
28#define CONFIG_HOSTNAME acadia
29#include "amcc-common.h"
30
Stefan Roese5d4a1792007-05-24 08:22:09 +020031/* Detect Acadia PLL input clock automatically via CPLD bit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032#define CONFIG_SYS_CLK_FREQ ((in8(CONFIG_SYS_CPLD_BASE + 0) == 0x0c) ? \
Stefan Roese5d4a1792007-05-24 08:22:09 +020033 66666666 : 33333000)
Stefan Roese16c0cc12007-03-21 13:39:57 +010034
Stefan Roese3cb86f32007-03-24 15:45:34 +010035#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
36#define CONFIG_MISC_INIT_F 1 /* Call misc_init_f */
Stefan Roese16c0cc12007-03-21 13:39:57 +010037
38#define CONFIG_NO_SERIAL_EEPROM
39/*#undef CONFIG_NO_SERIAL_EEPROM*/
40
41#ifdef CONFIG_NO_SERIAL_EEPROM
Stefan Roese16c0cc12007-03-21 13:39:57 +010042/*----------------------------------------------------------------------------
43 * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI,
44 * assuming a 66MHz input clock to the 405EZ.
45 *---------------------------------------------------------------------------*/
46/* #define PLLMR0_100_100_12 */
47#define PLLMR0_200_133_66
48/* #define PLLMR0_266_160_80 */
49/* #define PLLMR0_333_166_83 */
50#endif
51
52/*-----------------------------------------------------------------------
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_FLASH_BASE 0xfe000000
57#define CONFIG_SYS_CPLD_BASE 0x80000000
58#define CONFIG_SYS_NAND_ADDR 0xd0000000
59#define CONFIG_SYS_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */
Stefan Roese16c0cc12007-03-21 13:39:57 +010060
Stefan Roese3cb86f32007-03-24 15:45:34 +010061/*-----------------------------------------------------------------------
62 * Initial RAM & stack pointer
63 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_TEMP_STACK_OCM 1 /* OCM as init ram */
Stefan Roese3cb86f32007-03-24 15:45:34 +010065
66/* On Chip Memory location */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_OCM_DATA_ADDR 0xf8000000
68#define CONFIG_SYS_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */
69#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +020070#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
Stefan Roese3cb86f32007-03-24 15:45:34 +010071
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020072#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roese3cb86f32007-03-24 15:45:34 +010074
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020078#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
80#define CONFIG_SYS_BASE_BAUD 691200
Stefan Roese3cb86f32007-03-24 15:45:34 +010081
82/*-----------------------------------------------------------------------
83 * Environment
84 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020085#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
Stefan Roese16c0cc12007-03-21 13:39:57 +010086
Stefan Roese3cb86f32007-03-24 15:45:34 +010087/*-----------------------------------------------------------------------
88 * FLASH related
89 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020090#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020091#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roese3cb86f32007-03-24 15:45:34 +010092
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
94#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
95#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roese3cb86f32007-03-24 15:45:34 +010096
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
98#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese3cb86f32007-03-24 15:45:34 +010099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
101#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100102
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200103#ifdef CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200106#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100107
108/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200109#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
110#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese3cb86f32007-03-24 15:45:34 +0100111#endif
112
113/*-----------------------------------------------------------------------
114 * RAM (CRAM)
115 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_MBYTES_RAM 64 /* 64MB */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100117
118/*-----------------------------------------------------------------------
119 * I2C
120 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000121#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Stefan Roese3cb86f32007-03-24 15:45:34 +0100122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
124#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
125#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
126#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese3cb86f32007-03-24 15:45:34 +0100127
128/* I2C SYSMON (LM75, AD7414 is almost compatible) */
129#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
130#define CONFIG_DTT_AD7414 1 /* use AD7414 */
131#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DTT_MAX_TEMP 70
133#define CONFIG_SYS_DTT_LOW_TEMP -30
134#define CONFIG_SYS_DTT_HYSTERESIS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100135
Stefan Roese3cb86f32007-03-24 15:45:34 +0100136/*-----------------------------------------------------------------------
137 * Ethernet
138 *----------------------------------------------------------------------*/
Stefan Roese3cb86f32007-03-24 15:45:34 +0100139#define CONFIG_PHY_ADDR 0 /* PHY address */
Stefan Roesed1c1ba82008-05-08 10:48:58 +0200140#define CONFIG_HAS_ETH0 1
Stefan Roese3cb86f32007-03-24 15:45:34 +0100141
Stefan Roese490f2042008-06-06 15:55:03 +0200142/*
143 * Default environment variables
144 */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100145#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200146 CONFIG_AMCC_DEF_ENV \
Stefan Roese84a45d32009-09-11 17:09:45 +0200147 CONFIG_AMCC_DEF_ENV_POWERPC \
148 CONFIG_AMCC_DEF_ENV_PPC_OLD \
Stefan Roese490f2042008-06-06 15:55:03 +0200149 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100150 "kernel_addr=fff10000\0" \
151 "ramdisk_addr=fff20000\0" \
Stefan Roese16c0cc12007-03-21 13:39:57 +0100152 "kozio=bootm ffc60000\0" \
153 ""
Stefan Roese16c0cc12007-03-21 13:39:57 +0100154
Stefan Roese16c0cc12007-03-21 13:39:57 +0100155#define CONFIG_USB_OHCI
156#define CONFIG_USB_STORAGE
157
Stefan Roese16c0cc12007-03-21 13:39:57 +0100158/* Partitions */
159#define CONFIG_MAC_PARTITION
160#define CONFIG_DOS_PARTITION
161#define CONFIG_ISO_PARTITION
162
163#define CONFIG_SUPPORT_VFAT
164
Jon Loeliger0b361c92007-07-04 22:31:42 -0500165/*
Stefan Roese490f2042008-06-06 15:55:03 +0200166 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500167 */
Jon Loeliger0b361c92007-07-04 22:31:42 -0500168#define CONFIG_CMD_DTT
Jon Loeliger0b361c92007-07-04 22:31:42 -0500169#define CONFIG_CMD_NAND
Jon Loeliger0b361c92007-07-04 22:31:42 -0500170
Stefan Roese16c0cc12007-03-21 13:39:57 +0100171/*-----------------------------------------------------------------------
172 * NAND FLASH
173 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_MAX_NAND_DEVICE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
176#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
Stefan Roese16c0cc12007-03-21 13:39:57 +0100177
178/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100179 * External Bus Controller (EBC) Setup
Stefan Roese3cb86f32007-03-24 15:45:34 +0100180 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_NAND_CS 3
Stefan Roese3cb86f32007-03-24 15:45:34 +0100182/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_EBC_PB0AP 0x03337200
184#define CONFIG_SYS_EBC_PB0CR 0xfe0bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100185
Stefan Roesec440bfe2007-06-06 11:42:13 +0200186/* Memory Bank 3 (NAND-FLASH) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_EBC_PB3AP 0x018003c0
188#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1c000)
Stefan Roesec440bfe2007-06-06 11:42:13 +0200189
Stefan Roese3cb86f32007-03-24 15:45:34 +0100190/* Just initial configuration for CRAM. Will be changed in memory.c to sync mode*/
191/* Memory Bank 1 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192#define CONFIG_SYS_EBC_PB1AP 0x030400c0
193#define CONFIG_SYS_EBC_PB1CR 0x000bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100194
Stefan Roese3cb86f32007-03-24 15:45:34 +0100195/* Memory Bank 2 (CRAM) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_EBC_PB2AP 0x030400c0
197#define CONFIG_SYS_EBC_PB2CR 0x020bc000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100198
Stefan Roese3cb86f32007-03-24 15:45:34 +0100199/* Memory Bank 4 (CPLD) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_EBC_PB4AP 0x04006000
201#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_CPLD_BASE | 0x18000)
Stefan Roese16c0cc12007-03-21 13:39:57 +0100202
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#define CONFIG_SYS_EBC_CFG 0xf8400000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100204
205/*-----------------------------------------------------------------------
Stefan Roese3cb86f32007-03-24 15:45:34 +0100206 * GPIO Setup
207 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_GPIO_CRAM_CLK 8
209#define CONFIG_SYS_GPIO_CRAM_WAIT 9 /* GPIO-In */
210#define CONFIG_SYS_GPIO_CRAM_ADV 10
211#define CONFIG_SYS_GPIO_CRAM_CRE (32 + 21) /* GPIO-Out */
Stefan Roese3cb86f32007-03-24 15:45:34 +0100212
213/*-----------------------------------------------------------------------
Stefan Roese16c0cc12007-03-21 13:39:57 +0100214 * Definitions for GPIO_0 setup (PPC405EZ specific)
215 *
Stefan Roese5d4a1792007-05-24 08:22:09 +0200216 * GPIO0[0-2] - External Bus Controller CS_4 - CS_6 Outputs
217 * GPIO0[3] - NAND FLASH Controller CE3 (NFCE3) Output
Stefan Roese16c0cc12007-03-21 13:39:57 +0100218 * GPIO0[4] - External Bus Controller Hold Input
219 * GPIO0[5] - External Bus Controller Priority Input
220 * GPIO0[6] - External Bus Controller HLDA Output
221 * GPIO0[7] - External Bus Controller Bus Request Output
222 * GPIO0[8] - CRAM Clk Output
223 * GPIO0[9] - External Bus Controller Ready Input
224 * GPIO0[10] - CRAM Adv Output
225 * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled
226 * GPIO0[25] - External DMA Request Input
227 * GPIO0[26] - External DMA EOT I/O
228 * GPIO0[25] - External DMA Ack_n Output
229 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
230 * GPIO0[28-30] - Trace Outputs / PWM Inputs
231 * GPIO0[31] - PWM_8 I/O
232 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_GPIO0_TCR 0xC0A00000
234#define CONFIG_SYS_GPIO0_OSRL 0x50004400
235#define CONFIG_SYS_GPIO0_OSRH 0x02000055
236#define CONFIG_SYS_GPIO0_ISR1L 0x00001000
237#define CONFIG_SYS_GPIO0_ISR1H 0x00000055
238#define CONFIG_SYS_GPIO0_TSRL 0x02000000
239#define CONFIG_SYS_GPIO0_TSRH 0x00000055
Stefan Roese16c0cc12007-03-21 13:39:57 +0100240
241/*-----------------------------------------------------------------------
242 * Definitions for GPIO_1 setup (PPC405EZ specific)
243 *
244 * GPIO1[0-6] - PWM_9 to PWM_15 I/O
245 * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input
246 * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input
247 * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input
248 * GPIO1[10-12] - UART0 Control Inputs
249 * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input
250 * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output
251 * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input
252 * GPIO1[16] - SPI_SS_1_N Output
253 * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_GPIO1_TCR 0xFFFF8414
256#define CONFIG_SYS_GPIO1_OSRL 0x40000110
257#define CONFIG_SYS_GPIO1_OSRH 0x55455555
258#define CONFIG_SYS_GPIO1_ISR1L 0x15555445
259#define CONFIG_SYS_GPIO1_ISR1H 0x00000000
260#define CONFIG_SYS_GPIO1_TSRL 0x00000000
261#define CONFIG_SYS_GPIO1_TSRH 0x00000000
Stefan Roese16c0cc12007-03-21 13:39:57 +0100262
Stefan Roese16c0cc12007-03-21 13:39:57 +0100263#endif /* __CONFIG_H */