blob: b7c4b1096963ec72dcd195058af33d0ebc1acfcc [file] [log] [blame]
Masahiro Yamada5894ca02014-10-03 19:21:06 +09001/*
2 * Copyright (C) 2011-2014 Panasonic Corporation
3 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/io.h>
10#include <asm/arch/sg-regs.h>
11
12void sg_init(void)
13{
14 u32 tmp;
15
16 /* Set DDR size */
17 tmp = sg_memconf_val_ch0(CONFIG_SDRAM0_SIZE, CONFIG_DDR_NUM_CH0);
18 tmp |= sg_memconf_val_ch1(CONFIG_SDRAM1_SIZE, CONFIG_DDR_NUM_CH1);
19#if CONFIG_SDRAM0_BASE + CONFIG_SDRAM0_SIZE < CONFIG_SDRAM1_BASE
20 tmp |= SG_MEMCONF_SPARSEMEM;
21#endif
22 writel(tmp, SG_MEMCONF);
23
Masahiro Yamada89a7c772015-01-13 18:54:34 +090024 /* Input ports must be enabled before deasserting reset of cores */
Masahiro Yamada5894ca02014-10-03 19:21:06 +090025 tmp = readl(SG_IECTRL);
Masahiro Yamada44843742015-01-19 22:31:10 +090026 tmp |= 1 << 6;
Masahiro Yamada5894ca02014-10-03 19:21:06 +090027 writel(tmp, SG_IECTRL);
28}