| Vignesh Raghavendra | 53b04c6 | 2020-07-07 13:43:33 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com |
| 4 | * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> |
| 5 | */ |
| 6 | |
| 7 | #include <linux/kernel.h> |
| 8 | |
| 9 | #include "k3-psil-priv.h" |
| 10 | |
| 11 | #define PSIL_ETHERNET(x) \ |
| 12 | { \ |
| 13 | .thread_id = x, \ |
| 14 | .ep_config = { \ |
| 15 | .ep_type = PSIL_EP_NATIVE, \ |
| 16 | .pkt_mode = 1, \ |
| 17 | .needs_epib = 1, \ |
| 18 | .psd_size = 16, \ |
| 19 | }, \ |
| 20 | } |
| 21 | |
| 22 | /* PSI-L source thread IDs, used for RX (DMA_DEV_TO_MEM) */ |
| 23 | static struct psil_ep am654_src_ep_map[] = { |
| 24 | /* PRU_ICSSG0 */ |
| 25 | PSIL_ETHERNET(0x4100), |
| 26 | PSIL_ETHERNET(0x4101), |
| 27 | PSIL_ETHERNET(0x4102), |
| 28 | PSIL_ETHERNET(0x4103), |
| 29 | /* PRU_ICSSG1 */ |
| 30 | PSIL_ETHERNET(0x4200), |
| 31 | PSIL_ETHERNET(0x4201), |
| 32 | PSIL_ETHERNET(0x4202), |
| 33 | PSIL_ETHERNET(0x4203), |
| 34 | /* PRU_ICSSG2 */ |
| 35 | PSIL_ETHERNET(0x4300), |
| 36 | PSIL_ETHERNET(0x4301), |
| 37 | PSIL_ETHERNET(0x4302), |
| 38 | PSIL_ETHERNET(0x4303), |
| 39 | /* CPSW0 */ |
| 40 | PSIL_ETHERNET(0x7000), |
| 41 | }; |
| 42 | |
| 43 | /* PSI-L destination thread IDs, used for TX (DMA_MEM_TO_DEV) */ |
| 44 | static struct psil_ep am654_dst_ep_map[] = { |
| 45 | /* PRU_ICSSG0 */ |
| 46 | PSIL_ETHERNET(0xc100), |
| 47 | PSIL_ETHERNET(0xc101), |
| 48 | PSIL_ETHERNET(0xc102), |
| 49 | PSIL_ETHERNET(0xc103), |
| 50 | PSIL_ETHERNET(0xc104), |
| 51 | PSIL_ETHERNET(0xc105), |
| 52 | PSIL_ETHERNET(0xc106), |
| 53 | PSIL_ETHERNET(0xc107), |
| 54 | /* PRU_ICSSG1 */ |
| 55 | PSIL_ETHERNET(0xc200), |
| 56 | PSIL_ETHERNET(0xc201), |
| 57 | PSIL_ETHERNET(0xc202), |
| 58 | PSIL_ETHERNET(0xc203), |
| 59 | PSIL_ETHERNET(0xc204), |
| 60 | PSIL_ETHERNET(0xc205), |
| 61 | PSIL_ETHERNET(0xc206), |
| 62 | PSIL_ETHERNET(0xc207), |
| 63 | /* PRU_ICSSG2 */ |
| 64 | PSIL_ETHERNET(0xc300), |
| 65 | PSIL_ETHERNET(0xc301), |
| 66 | PSIL_ETHERNET(0xc302), |
| 67 | PSIL_ETHERNET(0xc303), |
| 68 | PSIL_ETHERNET(0xc304), |
| 69 | PSIL_ETHERNET(0xc305), |
| 70 | PSIL_ETHERNET(0xc306), |
| 71 | PSIL_ETHERNET(0xc307), |
| 72 | /* CPSW0 */ |
| 73 | PSIL_ETHERNET(0xf000), |
| 74 | PSIL_ETHERNET(0xf001), |
| 75 | PSIL_ETHERNET(0xf002), |
| 76 | PSIL_ETHERNET(0xf003), |
| 77 | PSIL_ETHERNET(0xf004), |
| 78 | PSIL_ETHERNET(0xf005), |
| 79 | PSIL_ETHERNET(0xf006), |
| 80 | PSIL_ETHERNET(0xf007), |
| 81 | }; |
| 82 | |
| 83 | struct psil_ep_map am654_ep_map = { |
| 84 | .name = "am654", |
| 85 | .src = am654_src_ep_map, |
| 86 | .src_count = ARRAY_SIZE(am654_src_ep_map), |
| 87 | .dst = am654_dst_ep_map, |
| 88 | .dst_count = ARRAY_SIZE(am654_dst_ep_map), |
| 89 | }; |