blob: 04fda4a69f1bbd9e2bf9f25daecb33d4ead78e42 [file] [log] [blame]
Heiko Schocher2605e902007-02-16 07:57:42 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
29#include <pci.h>
30#include <asm/processor.h>
31
32#if defined(CONFIG_OF_FLAT_TREE)
33#include <ft_build.h>
34#endif
35
36
37#define SDRAM_DDR 0
38#if 1
39/* Settings Icecube */
40#define SDRAM_MODE 0x00CD0000
41#define SDRAM_CONTROL 0x504F0000
42#define SDRAM_CONFIG1 0xD2322800
43#define SDRAM_CONFIG2 0x8AD70000
44#else
45/*Settings Jupiter UB 1.0.0 */
46#define SDRAM_MODE 0x008D0000
47#define SDRAM_CONTROL 0xD04F0000
48#define SDRAM_CONFIG1 0xf7277f00
49#define SDRAM_CONFIG2 0x88b70004
50#endif
51
52#ifndef CFG_RAMBOOT
53static void sdram_start (int hi_addr)
54{
55 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
56
57 /* unlock mode register */
58 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
59 __asm__ volatile ("sync");
60
61 /* precharge all banks */
62 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
63 __asm__ volatile ("sync");
64
65#if SDRAM_DDR
66 /* set mode register: extended mode */
67 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
68 __asm__ volatile ("sync");
69
70 /* set mode register: reset DLL */
71 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
72 __asm__ volatile ("sync");
73#endif
74
75 /* precharge all banks */
76 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
77 __asm__ volatile ("sync");
78
79 /* auto refresh */
80 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
81 __asm__ volatile ("sync");
82
83 /* set mode register */
84 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
85 __asm__ volatile ("sync");
86
87 /* normal operation */
88 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
89 __asm__ volatile ("sync");
90}
91#endif
92
93/*
94 * ATTENTION: Although partially referenced initdram does NOT make real use
95 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
96 * is something else than 0x00000000.
97 */
98
99long int initdram (int board_type)
100{
101 ulong dramsize = 0;
102 ulong dramsize2 = 0;
103 uint svr, pvr;
104
105#ifndef CFG_RAMBOOT
106 ulong test1, test2;
107
108 /* setup SDRAM chip selects */
109 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
110 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
111 __asm__ volatile ("sync");
112
113 /* setup config registers */
114 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
115 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
116 __asm__ volatile ("sync");
117
118#if SDRAM_DDR
119 /* set tap delay */
120 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
121 __asm__ volatile ("sync");
122#endif
123
124 /* find RAM size using SDRAM CS0 only */
125 sdram_start(0);
126 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
127 sdram_start(1);
128 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
129 if (test1 > test2) {
130 sdram_start(0);
131 dramsize = test1;
132 } else {
133 dramsize = test2;
134 }
135
136 /* memory smaller than 1MB is impossible */
137 if (dramsize < (1 << 20)) {
138 dramsize = 0;
139 }
140
141 /* set SDRAM CS0 size according to the amount of RAM found */
142 if (dramsize > 0) {
143 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
144 } else {
145 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
146 }
147
148 /* let SDRAM CS1 start right after CS0 */
149 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
150
151 /* find RAM size using SDRAM CS1 only */
152 if (!dramsize)
153 sdram_start(0);
154 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
155 if (!dramsize) {
156 sdram_start(1);
157 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
158 }
159 if (test1 > test2) {
160 sdram_start(0);
161 dramsize2 = test1;
162 } else {
163 dramsize2 = test2;
164 }
165
166 /* memory smaller than 1MB is impossible */
167 if (dramsize2 < (1 << 20)) {
168 dramsize2 = 0;
169 }
170
171 /* set SDRAM CS1 size according to the amount of RAM found */
172 if (dramsize2 > 0) {
173 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
174 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
175 } else {
176 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
177 }
178
179#else /* CFG_RAMBOOT */
180
181 /* retrieve size of memory connected to SDRAM CS0 */
182 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
183 if (dramsize >= 0x13) {
184 dramsize = (1 << (dramsize - 0x13)) << 20;
185 } else {
186 dramsize = 0;
187 }
188
189 /* retrieve size of memory connected to SDRAM CS1 */
190 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
191 if (dramsize2 >= 0x13) {
192 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
193 } else {
194 dramsize2 = 0;
195 }
196
197#endif /* CFG_RAMBOOT */
198
199 /*
200 * On MPC5200B we need to set the special configuration delay in the
201 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
202 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
203 *
204 * "The SDelay should be written to a value of 0x00000004. It is
205 * required to account for changes caused by normal wafer processing
206 * parameters."
207 */
208 svr = get_svr();
209 pvr = get_pvr();
210 if ((SVR_MJREV(svr) >= 2) &&
211 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
212
213 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
214 __asm__ volatile ("sync");
215 }
216
217 return dramsize + dramsize2;
218}
219
220int checkboard (void)
221{
222 puts ("Board: Sauter (Jupiter)\n");
223 return 0;
224}
225
226void flash_preinit(void)
227{
228 /*
229 * Now, when we are in RAM, enable flash write
230 * access for detection process.
231 * Note that CS_BOOT cannot be cleared when
232 * executing in flash.
233 */
234#if defined(CONFIG_MGT5100)
235 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
236 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
237#endif
238 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
239}
240
241int board_early_init_r (void)
242{
243 flash_preinit ();
244 return 0;
245}
246
247void flash_afterinit(ulong size)
248{
249 if (size == 0x1000000) { /* adjust mapping */
250 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
251 START_REG(CFG_BOOTCS_START | size);
252 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
253 STOP_REG(CFG_BOOTCS_START | size, size);
254 }
255#if defined(CONFIG_MPC5200)
256 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
257 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
258#endif
259}
260
261int update_flash_size (int flash_size)
262{
263 flash_afterinit (flash_size);
264 return 0;
265}
266
267int board_early_init_f (void)
268{
269 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
270 return 0;
271}
272
273#ifdef CONFIG_PCI
274static struct pci_controller hose;
275
276extern void pci_mpc5xxx_init(struct pci_controller *);
277
278void pci_init_board(void)
279{
280 pci_mpc5xxx_init(&hose);
281}
282#endif
283
284#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
285
286void init_ide_reset (void)
287{
288 debug ("init_ide_reset\n");
289
290 /* Configure PSC1_4 as GPIO output for ATA reset */
291 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
292 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
293 /* Deassert reset */
294 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
295}
296
297void ide_set_reset (int idereset)
298{
299 debug ("ide_reset(%d)\n", idereset);
300
301 if (idereset) {
302 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
303 /* Make a delay. MPC5200 spec says 25 usec min */
304 udelay(500000);
305 } else {
306 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
307 }
308}
309#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
310
311#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
312void
313ft_board_setup(void *blob, bd_t *bd)
314{
315 ft_cpu_setup(blob, bd);
316}
317#endif