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Stefan Roese995b72d2012-05-30 22:59:08 +00001/*
Patrice Chotarde36591c2017-10-23 09:54:00 +02002 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
3 * Author(s): Vipin Kumar, <vipin.kumar@st.com> for STMicroelectronics.
Stefan Roese995b72d2012-05-30 22:59:08 +00004 *
Stefan Roese2fbdbda2015-08-18 09:27:17 +02005 * Copyright (C) 2012, 2015 Stefan Roese <sr@denx.de>
Stefan Roese995b72d2012-05-30 22:59:08 +00006 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese995b72d2012-05-30 22:59:08 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/*
14 * High Level Configuration Options
15 * (easy to change)
16 */
17#define CONFIG_SPEAR600 /* SPEAr600 SoC */
18#define CONFIG_X600 /* on X600 board */
19
20#include <asm/arch/hardware.h>
21
22/* Timer, HZ specific defines */
Stefan Roese995b72d2012-05-30 22:59:08 +000023#define CONFIG_SYS_HZ_CLOCK 8300000
24
25#define CONFIG_SYS_TEXT_BASE 0x00800040
26#define CONFIG_SYS_FLASH_BASE 0xf8000000
27/* Reserve 8KiB for SPL */
28#define CONFIG_SPL_PAD_TO 8192 /* decimal for 'dd' */
29#define CONFIG_SYS_SPL_LEN CONFIG_SPL_PAD_TO
30#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
31 CONFIG_SYS_SPL_LEN)
Stefan Roese285e2662015-08-18 09:27:20 +020032#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
Stefan Roese995b72d2012-05-30 22:59:08 +000033#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
34#define CONFIG_SYS_MONITOR_LEN 0x60000
35
Stefan Roese995b72d2012-05-30 22:59:08 +000036/* Serial Configuration (PL011) */
37#define CONFIG_SYS_SERIAL0 0xD0000000
38#define CONFIG_SYS_SERIAL1 0xD0080000
39#define CONFIG_PL01x_PORTS { (void *)CONFIG_SYS_SERIAL0, \
40 (void *)CONFIG_SYS_SERIAL1 }
41#define CONFIG_PL011_SERIAL
42#define CONFIG_PL011_CLOCK (48 * 1000 * 1000)
43#define CONFIG_CONS_INDEX 0
Stefan Roese995b72d2012-05-30 22:59:08 +000044#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, \
45 57600, 115200 }
46#define CONFIG_SYS_LOADS_BAUD_CHANGE
47
48/* NOR FLASH config options */
49#define CONFIG_ST_SMI
50#define CONFIG_SYS_MAX_FLASH_BANKS 1
51#define CONFIG_SYS_FLASH_BANK_SIZE 0x01000000
52#define CONFIG_SYS_FLASH_ADDR_BASE { CONFIG_SYS_FLASH_BASE }
53#define CONFIG_SYS_MAX_FLASH_SECT 128
54#define CONFIG_SYS_FLASH_EMPTY_INFO
55#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * CONFIG_SYS_HZ)
56#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * CONFIG_SYS_HZ)
57
58/* NAND FLASH config options */
59#define CONFIG_NAND_FSMC
60#define CONFIG_SYS_NAND_SELF_INIT
61#define CONFIG_SYS_MAX_NAND_DEVICE 1
62#define CONFIG_SYS_NAND_BASE CONFIG_FSMC_NAND_BASE
63#define CONFIG_MTD_ECC_SOFT
64#define CONFIG_SYS_FSMC_NAND_8BIT
65#define CONFIG_SYS_NAND_ONFI_DETECTION
Stefan Roese0ddc5a22015-09-02 11:10:59 +020066#define CONFIG_NAND_ECC_BCH
Stefan Roese995b72d2012-05-30 22:59:08 +000067
68/* UBI/UBI config options */
69#define CONFIG_MTD_DEVICE
70#define CONFIG_MTD_PARTITIONS
Stefan Roese995b72d2012-05-30 22:59:08 +000071
72/* Ethernet config options */
73#define CONFIG_MII
Stefan Roese995b72d2012-05-30 22:59:08 +000074#define CONFIG_PHY_RESET_DELAY 10000 /* in usec */
Stefan Roese995b72d2012-05-30 22:59:08 +000075#define CONFIG_PHY_ADDR 0 /* PHY address */
Stefan Roese995b72d2012-05-30 22:59:08 +000076
77#define CONFIG_SPEAR_GPIO
78
79/* I2C config options */
Stefan Roese678398b2014-10-28 12:12:00 +010080#define CONFIG_SYS_I2C
Alexey Brodkinf93f5892014-02-10 12:20:11 +040081#define CONFIG_SYS_I2C_BASE 0xD0200000
Stefan Roese995b72d2012-05-30 22:59:08 +000082#define CONFIG_SYS_I2C_SPEED 400000
83#define CONFIG_SYS_I2C_SLAVE 0x02
84#define CONFIG_I2C_CHIPADDRESS 0x50
85
86#define CONFIG_RTC_M41T62 1
87#define CONFIG_SYS_I2C_RTC_ADDR 0x68
88
89/* FPGA config options */
90#define CONFIG_FPGA
91#define CONFIG_FPGA_XILINX
92#define CONFIG_FPGA_SPARTAN3
93#define CONFIG_FPGA_COUNT 1
94
Stefan Roese285e2662015-08-18 09:27:20 +020095/* USB EHCI options */
Stefan Roese285e2662015-08-18 09:27:20 +020096#define CONFIG_USB_EHCI_SPEAR
Stefan Roese285e2662015-08-18 09:27:20 +020097#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
98
Stefan Roese285e2662015-08-18 09:27:20 +020099/* Filesystem support (for USB key) */
100#define CONFIG_SUPPORT_VFAT
Stefan Roese285e2662015-08-18 09:27:20 +0200101
Stefan Roese995b72d2012-05-30 22:59:08 +0000102
Stefan Roese995b72d2012-05-30 22:59:08 +0000103/*
104 * U-Boot Environment placing definitions.
105 */
106#define CONFIG_ENV_SECT_SIZE 0x00010000
107#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
108 CONFIG_SYS_MONITOR_LEN)
109#define CONFIG_ENV_SIZE 0x02000
110#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \
111 CONFIG_ENV_SECT_SIZE)
112#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
113
114/* Miscellaneous configurable options */
115#define CONFIG_ARCH_CPU_INIT
Stefan Roese995b72d2012-05-30 22:59:08 +0000116#define CONFIG_BOOT_PARAMS_ADDR 0x00000100
117#define CONFIG_CMDLINE_TAG
Stefan Roese995b72d2012-05-30 22:59:08 +0000118#define CONFIG_SETUP_MEMORY_TAGS
119#define CONFIG_MISC_INIT_R
Stefan Roese995b72d2012-05-30 22:59:08 +0000120#define CONFIG_MX_CYCLIC /* enable mdc/mwc commands */
Stefan Roese995b72d2012-05-30 22:59:08 +0000121
122#define CONFIG_SYS_MEMTEST_START 0x00800000
123#define CONFIG_SYS_MEMTEST_END 0x04000000
Stefan Roese285e2662015-08-18 09:27:20 +0200124#define CONFIG_SYS_MALLOC_LEN (8 << 20)
Stefan Roese995b72d2012-05-30 22:59:08 +0000125#define CONFIG_SYS_LONGHELP
Stefan Roese995b72d2012-05-30 22:59:08 +0000126#define CONFIG_CMDLINE_EDITING
Stefan Roese285e2662015-08-18 09:27:20 +0200127#define CONFIG_AUTO_COMPLETE
Stefan Roese995b72d2012-05-30 22:59:08 +0000128#define CONFIG_SYS_LOAD_ADDR 0x00800000
Stefan Roese995b72d2012-05-30 22:59:08 +0000129
130/* Use last 2 lwords in internal SRAM for bootcounter */
131#define CONFIG_BOOTCOUNT_LIMIT
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200132#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SRAM_BASE + \
133 CONFIG_SRAM_SIZE)
Stefan Roese995b72d2012-05-30 22:59:08 +0000134
135#define CONFIG_HOSTNAME x600
136#define CONFIG_UBI_PART ubi0
137#define CONFIG_UBIFS_VOLUME rootfs
138
Stefan Roese995b72d2012-05-30 22:59:08 +0000139#define CONFIG_EXTRA_ENV_SETTINGS \
140 "u-boot_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200141 "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.spr\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000142 "load=tftp ${u-boot_addr} ${u-boot}\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200143 "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
144 " +${filesize};" \
145 "erase " __stringify(CONFIG_SYS_MONITOR_BASE) " +${filesize};" \
146 "cp.b ${u-boot_addr} " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000147 " ${filesize};" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200148 "protect on " __stringify(CONFIG_SYS_MONITOR_BASE) \
Stefan Roese995b72d2012-05-30 22:59:08 +0000149 " +${filesize}\0" \
150 "upd=run load update\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200151 "ubifs=" __stringify(CONFIG_HOSTNAME) "/ubifs.img\0" \
152 "part=" __stringify(CONFIG_UBI_PART) "\0" \
153 "vol=" __stringify(CONFIG_UBIFS_VOLUME) "\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000154 "load_ubifs=tftp ${kernel_addr} ${ubifs}\0" \
155 "update_ubifs=ubi part ${part};ubi write ${kernel_addr} ${vol}" \
156 " ${filesize}\0" \
157 "upd_ubifs=run load_ubifs update_ubifs\0" \
158 "init_ubifs=nand erase.part ubi0;ubi part ${part};" \
159 "ubi create ${vol} 4000000\0" \
160 "netdev=eth0\0" \
161 "rootpath=/opt/eldk-4.2/arm\0" \
162 "nfsargs=setenv bootargs root=/dev/nfs rw " \
163 "nfsroot=${serverip}:${rootpath}\0" \
164 "ramargs=setenv bootargs root=/dev/ram rw\0" \
165 "boot_part=0\0" \
166 "altbootcmd=if test $boot_part -eq 0;then " \
167 "echo Switching to partition 1!;" \
168 "setenv boot_part 1;" \
169 "else; " \
170 "echo Switching to partition 0!;" \
171 "setenv boot_part 0;" \
172 "fi;" \
173 "saveenv;boot\0" \
174 "ubifsargs=set bootargs ubi.mtd=ubi${boot_part} " \
175 "root=ubi0:rootfs rootfstype=ubifs\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200176 "kernel=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000177 "kernel_fs=/boot/uImage \0" \
178 "kernel_addr=1000000\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200179 "dtb=" __stringify(CONFIG_HOSTNAME) "/" \
180 __stringify(CONFIG_HOSTNAME) ".dtb\0" \
181 "dtb_fs=/boot/" __stringify(CONFIG_HOSTNAME) ".dtb\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000182 "dtb_addr=1800000\0" \
183 "load_kernel=tftp ${kernel_addr} ${kernel}\0" \
184 "load_dtb=tftp ${dtb_addr} ${dtb}\0" \
185 "addip=setenv bootargs ${bootargs} " \
186 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
187 ":${hostname}:${netdev}:off panic=1\0" \
188 "addcon=setenv bootargs ${bootargs} console=ttyAMA0," \
189 "${baudrate}\0" \
190 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
191 "net_nfs=run load_dtb load_kernel; " \
192 "run nfsargs addip addcon addmtd addmisc;" \
193 "bootm ${kernel_addr} - ${dtb_addr}\0" \
Tom Rini43ede0b2017-10-22 17:55:07 -0400194 "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
195 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000196 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip" \
197 " addcon addmisc addmtd;" \
198 "bootm ${kernel_addr} - ${dtb_addr}\0" \
Joe Hershberger949a7712012-11-01 16:54:18 +0000199 "ubifs_mount=ubi part ubi${boot_part};ubifsmount ubi:rootfs\0" \
Stefan Roese995b72d2012-05-30 22:59:08 +0000200 "ubifs_load=ubifsload ${kernel_addr} ${kernel_fs};" \
201 "ubifsload ${dtb_addr} ${dtb_fs};\0" \
202 "nand_ubifs=run ubifs_mount ubifs_load ubifsargs addip addcon " \
203 "addmtd addmisc;bootm ${kernel_addr} - ${dtb_addr}\0" \
204 "bootcmd=run nand_ubifs\0" \
205 "\0"
206
Stefan Roese995b72d2012-05-30 22:59:08 +0000207/* Physical Memory Map */
208#define CONFIG_NR_DRAM_BANKS 1
209#define PHYS_SDRAM_1 0x00000000
210#define PHYS_SDRAM_1_MAXSIZE 0x40000000
211
212#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200213#define CONFIG_SRAM_BASE 0xd2800000
214/* Preserve the last 2 lwords for the boot-counter */
215#define CONFIG_SRAM_SIZE ((8 << 10) - 0x8)
216#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SRAM_BASE
217#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SRAM_SIZE
Stefan Roese995b72d2012-05-30 22:59:08 +0000218
219#define CONFIG_SYS_INIT_SP_OFFSET \
220 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
221
222#define CONFIG_SYS_INIT_SP_ADDR \
223 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
224
225/*
226 * SPL related defines
227 */
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200228#define CONFIG_SPL_TEXT_BASE 0xd2800b00
229#define CONFIG_SPL_MAX_SIZE (CONFIG_SRAM_SIZE - 0xb00)
Stefan Roese995b72d2012-05-30 22:59:08 +0000230#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/arm926ejs/spear"
Stefan Roese995b72d2012-05-30 22:59:08 +0000231
Stefan Roese2fbdbda2015-08-18 09:27:17 +0200232#define CONFIG_SPL_FRAMEWORK
Stefan Roese995b72d2012-05-30 22:59:08 +0000233
234/*
235 * Please select/define only one of the following
236 * Each definition corresponds to a supported DDR chip.
237 * DDR configuration is based on the following selection
238 */
239#define CONFIG_DDR_MT47H64M16 1
240#define CONFIG_DDR_MT47H32M16 0
241#define CONFIG_DDR_MT47H128M8 0
242
243/*
244 * Synchronous/Asynchronous operation of DDR
245 *
246 * Select CONFIG_DDR_2HCLK for DDR clk = 333MHz, synchronous operation
247 * Select CONFIG_DDR_HCLK for DDR clk = 166MHz, synchronous operation
248 * Select CONFIG_DDR_PLL2 for DDR clk = PLL2, asynchronous operation
249 */
250#define CONFIG_DDR_2HCLK 1
251#define CONFIG_DDR_HCLK 0
252#define CONFIG_DDR_PLL2 0
253
254/*
255 * xxx_BOOT_SUPPORTED macro defines whether a booting type is supported
256 * or not. Modify/Add to only these macros to define new boot types
257 */
258#define USB_BOOT_SUPPORTED 0
259#define PCIE_BOOT_SUPPORTED 0
260#define SNOR_BOOT_SUPPORTED 1
261#define NAND_BOOT_SUPPORTED 1
262#define PNOR_BOOT_SUPPORTED 0
263#define TFTP_BOOT_SUPPORTED 0
264#define UART_BOOT_SUPPORTED 0
265#define SPI_BOOT_SUPPORTED 0
266#define I2C_BOOT_SUPPORTED 0
267#define MMC_BOOT_SUPPORTED 0
268
269#endif /* __CONFIG_H */