blob: 1d6d29736ffb65ef026eaec610b325bf9dbe49dc [file] [log] [blame]
wdenk4e5ca3e2003-12-08 01:34:36 +00001/*
wdenkbf9e3b32004-02-12 00:47:09 +00002 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
3 *
4 * (C) Copyright 2000
wdenk4e5ca3e2003-12-08 01:34:36 +00005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
wdenkbf9e3b32004-02-12 00:47:09 +000017 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
wdenk4e5ca3e2003-12-08 01:34:36 +000018 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27
wdenkbf9e3b32004-02-12 00:47:09 +000028#include <asm/mcftimer.h>
wdenk4e5ca3e2003-12-08 01:34:36 +000029
wdenkbf9e3b32004-02-12 00:47:09 +000030#ifdef CONFIG_M5272
31#include <asm/m5272.h>
32#include <asm/immap_5272.h>
33#endif
wdenk4e5ca3e2003-12-08 01:34:36 +000034
wdenkbf9e3b32004-02-12 00:47:09 +000035#ifdef CONFIG_M5282
36#include <asm/m5282.h>
37#endif
38
stroesecd42dee2004-12-16 17:56:09 +000039#ifdef CONFIG_M5249
40#include <asm/m5249.h>
41#include <asm/immap_5249.h>
42#endif
43
wdenkbf9e3b32004-02-12 00:47:09 +000044
45static ulong timestamp;
46#ifdef CONFIG_M5282
47static unsigned short lastinc;
48#endif
49
50
51#if defined(CONFIG_M5272)
wdenk4e5ca3e2003-12-08 01:34:36 +000052/*
wdenkbf9e3b32004-02-12 00:47:09 +000053 * We use timer 3 which is running with a period of 1 us
wdenk4e5ca3e2003-12-08 01:34:36 +000054 */
55void udelay(unsigned long usec)
56{
wdenkbf9e3b32004-02-12 00:47:09 +000057 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE3);
58 uint start, now, tmp;
wdenk4e5ca3e2003-12-08 01:34:36 +000059
wdenkbf9e3b32004-02-12 00:47:09 +000060 while (usec > 0) {
61 if (usec > 65000)
62 tmp = 65000;
63 else
64 tmp = usec;
65 usec = usec - tmp;
66
67 /* Set up TIMER 3 as timebase clock */
68 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
69 timerp->timer_tcn = 0;
70 /* set period to 1 us */
71 timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
72 MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
73
74 start = now = timerp->timer_tcn;
75 while (now < start + tmp)
76 now = timerp->timer_tcn;
77 }
wdenk4e5ca3e2003-12-08 01:34:36 +000078}
79
wdenkbf9e3b32004-02-12 00:47:09 +000080void mcf_timer_interrupt (void * not_used){
81 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
82 volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
wdenk4e5ca3e2003-12-08 01:34:36 +000083
wdenkbf9e3b32004-02-12 00:47:09 +000084 /* check for timer 4 interrupts */
85 if ((intp->int_isr & 0x01000000) != 0) {
86 return;
87 }
88
89 /* reset timer */
90 timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
91 timestamp ++;
92}
93
94void timer_init (void) {
95 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE4);
96 volatile intctrl_t *intp = (intctrl_t *) (CFG_MBAR + MCFSIM_ICR1);
97
98 timestamp = 0;
99
100 /* Set up TIMER 4 as clock */
101 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
102
103 /* initialize and enable timer 4 interrupt */
104 irq_install_handler (72, mcf_timer_interrupt, 0);
105 intp->int_icr1 |= 0x0000000d;
106
107 timerp->timer_tcn = 0;
108 timerp->timer_trr = 1000; /* Interrupt every ms */
109 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
110 timerp->timer_tmr = (((CFG_CLK / 1000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
111 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
112}
113
114void reset_timer (void)
wdenk4e5ca3e2003-12-08 01:34:36 +0000115{
wdenkbf9e3b32004-02-12 00:47:09 +0000116 timestamp = 0;
wdenk4e5ca3e2003-12-08 01:34:36 +0000117}
118
wdenkbf9e3b32004-02-12 00:47:09 +0000119ulong get_timer (ulong base)
wdenk4e5ca3e2003-12-08 01:34:36 +0000120{
wdenkbf9e3b32004-02-12 00:47:09 +0000121 return (timestamp - base);
wdenk4e5ca3e2003-12-08 01:34:36 +0000122}
123
wdenkbf9e3b32004-02-12 00:47:09 +0000124void set_timer (ulong t)
125{
126 timestamp = t;
127}
128#endif
129
130#if defined(CONFIG_M5282)
131
132void udelay(unsigned long usec)
133{
wdenk50712ba2005-04-03 23:35:57 +0000134 volatile unsigned short *timerp;
135 uint tmp;
136
137 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3);
wdenk3c2b3d42005-04-05 23:32:21 +0000138
wdenk50712ba2005-04-03 23:35:57 +0000139 while (usec > 0) {
140 if (usec > 65000)
141 tmp = 65000;
142 else
143 tmp = usec;
144 usec = usec - tmp;
145
146 /* Set up TIMER 3 as timebase clock */
147 timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
148 timerp[MCFTIMER_PMR] = 0;
149 /* set period to 1 us */
150 timerp[MCFTIMER_PCSR] =
151 (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
152
wdenk3c2b3d42005-04-05 23:32:21 +0000153 timerp[MCFTIMER_PMR] = tmp;
wdenk50712ba2005-04-03 23:35:57 +0000154 while (timerp[MCFTIMER_PCNTR] > 0);
155 }
wdenkbf9e3b32004-02-12 00:47:09 +0000156}
157
158void timer_init (void)
159{
160 volatile unsigned short *timerp;
161
162 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
163 timestamp = 0;
164
165 /* Set up TIMER 4 as poll clock */
166 timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW;
167 timerp[MCFTIMER_PMR] = lastinc = 0;
168 timerp[MCFTIMER_PCSR] =
169 (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW;
170}
171
172void set_timer (ulong t)
173{
174 volatile unsigned short *timerp;
175
176 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
177 timestamp = 0;
178 timerp[MCFTIMER_PMR] = lastinc = 0;
179}
180
181ulong get_timer (ulong base)
182{
183 unsigned short now, diff;
184 volatile unsigned short *timerp;
185
186 timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE4);
187 now = timerp[MCFTIMER_PCNTR];
188 diff = -(now - lastinc);
189
190 timestamp += diff;
191 lastinc = now;
192 return timestamp - base;
193}
194
195void wait_ticks (unsigned long ticks)
196{
197 set_timer (0);
198 while (get_timer (0) < ticks);
199}
200#endif
wdenk70f05ac2004-06-09 15:24:18 +0000201
202
stroesecd42dee2004-12-16 17:56:09 +0000203#if defined(CONFIG_M5249)
204/*
205 * We use timer 1 which is running with a period of 1 us
206 */
207void udelay(unsigned long usec)
208{
209 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1);
210 uint start, now, tmp;
211
212 while (usec > 0) {
213 if (usec > 65000)
214 tmp = 65000;
215 else
216 tmp = usec;
217 usec = usec - tmp;
218
219 /* Set up TIMER 1 as timebase clock */
220 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
221 timerp->timer_tcn = 0;
222 /* set period to 1 us */
223 /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
224 timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
225 MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE;
226
227 start = now = timerp->timer_tcn;
228 while (now < start + tmp)
229 now = timerp->timer_tcn;
230 }
231}
232
233void mcf_timer_interrupt (void * not_used){
234 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
235
236 /* check for timer 2 interrupts */
237 if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) {
238 return;
239 }
240
241 /* reset timer */
242 timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF;
243 timestamp ++;
244}
245
246void timer_init (void) {
247 volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2);
248
249 timestamp = 0;
250
251 /* Set up TIMER 2 as clock */
252 timerp->timer_tmr = MCFTIMER_TMR_DISABLE;
253
254 /* initialize and enable timer 2 interrupt */
255 irq_install_handler (31, mcf_timer_interrupt, 0);
256 mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400);
257 mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3);
258
259 timerp->timer_tcn = 0;
260 timerp->timer_trr = 1000; /* Interrupt every ms */
261 /* set a period of 1us, set timer mode to restart and enable timer and interrupt */
262 /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */
263 timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 |
264 MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE;
265}
266
267void reset_timer (void)
268{
269 timestamp = 0;
270}
271
272ulong get_timer (ulong base)
273{
274 return (timestamp - base);
275}
276
277void set_timer (ulong t)
278{
279 timestamp = t;
280}
281#endif
282
283
wdenk70f05ac2004-06-09 15:24:18 +0000284/*
285 * This function is derived from PowerPC code (read timebase as long long).
286 * On M68K it just returns the timer value.
287 */
288unsigned long long get_ticks(void)
289{
290 return get_timer(0);
291}
292
293/*
294 * This function is derived from PowerPC code (timebase clock frequency).
295 * On M68K it returns the number of timer ticks per second.
296 */
297ulong get_tbclk (void)
298{
299 ulong tbclk;
300 tbclk = CFG_HZ;
301 return tbclk;
302}