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wdenk42d1f032003-10-15 23:53:47 +00001/*
2 * Adapted for Motorola MPC8560 chips
3 * Xianghua Xiao <x.xiao@motorola.com>
4 *
5 * This file is based on "arch/ppc/8260_io/commproc.c" - here is it's
6 * copyright notice:
7 *
8 * General Purpose functions for the global management of the
9 * 8220 Communication Processor Module.
10 * Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
11 * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
12 * 2.3.99 Updates
13 * Copyright (c) 2003 Motorola,Inc.
14 *
15 * In addition to the individual control of the communication
16 * channels, there are a few functions that globally affect the
17 * communication processor.
18 *
19 * Buffer descriptors must be allocated from the dual ported memory
20 * space. The allocator for that is here. When the communication
21 * process is reset, we reclaim the memory available. There is
22 * currently no deallocator for this memory.
23 */
24#include <common.h>
25#include <asm/cpm_85xx.h>
26
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050027#if defined(CONFIG_CPM2)
wdenk42d1f032003-10-15 23:53:47 +000028/*
29 * because we have stack and init data in dual port ram
30 * we must reduce the size
31 */
32#undef CPM_DATAONLY_SIZE
33#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
34
35void
36m8560_cpm_reset(void)
37{
38 DECLARE_GLOBAL_DATA_PTR;
39
40 volatile immap_t *immr = (immap_t *)CFG_IMMR;
41 volatile ulong count;
42
43 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
44
45 /* Reclaim the DP memory for our use.
46 */
47 gd->dp_alloc_base = CPM_DATAONLY_BASE;
48 gd->dp_alloc_top = gd->dp_alloc_base + CPM_DATAONLY_SIZE;
49
50 /*
51 * Reset CPM
52 */
53 immr->im_cpm.im_cpm_cp.cpcr = CPM_CR_RST;
54 count = 0;
55 do { /* Spin until command processed */
56 __asm__ __volatile__ ("eieio");
57 } while ((immr->im_cpm.im_cpm_cp.cpcr & CPM_CR_FLG) && ++count < 1000000);
58}
59
60/* Allocate some memory from the dual ported ram.
61 * To help protocols with object alignment restrictions, we do that
62 * if they ask.
63 */
64uint
65m8560_cpm_dpalloc(uint size, uint align)
66{
67 DECLARE_GLOBAL_DATA_PTR;
68
69 volatile immap_t *immr = (immap_t *)CFG_IMMR;
70 uint retloc;
71 uint align_mask, off;
72 uint savebase;
73
74 align_mask = align - 1;
75 savebase = gd->dp_alloc_base;
76
77 if ((off = (gd->dp_alloc_base & align_mask)) != 0)
78 gd->dp_alloc_base += (align - off);
79
80 if ((off = size & align_mask) != 0)
81 size += align - off;
82
83 if ((gd->dp_alloc_base + size) >= gd->dp_alloc_top) {
84 gd->dp_alloc_base = savebase;
85 panic("m8560_cpm_dpalloc: ran out of dual port ram!");
86 }
87
88 retloc = gd->dp_alloc_base;
89 gd->dp_alloc_base += size;
90
91 memset((void *)&(immr->im_cpm.im_dprambase[retloc]), 0, size);
92
93 return(retloc);
94}
95
96/* We also own one page of host buffer space for the allocation of
97 * UART "fifos" and the like.
98 */
99uint
100m8560_cpm_hostalloc(uint size, uint align)
101{
102 /* the host might not even have RAM yet - just use dual port RAM */
103 return (m8560_cpm_dpalloc(size, align));
104}
105
106/* Set a baud rate generator. This needs lots of work. There are
107 * eight BRGs, which can be connected to the CPM channels or output
108 * as clocks. The BRGs are in two different block of internal
109 * memory mapped space.
110 * The baud rate clock is the system clock divided by something.
111 * It was set up long ago during the initial boot phase and is
112 * is given to us.
113 * Baud rate clocks are zero-based in the driver code (as that maps
114 * to port numbers). Documentation uses 1-based numbering.
115 */
116#define BRG_INT_CLK gd->brg_clk
117#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
118
119/* This function is used by UARTS, or anything else that uses a 16x
120 * oversampled clock.
121 */
122void
123m8560_cpm_setbrg(uint brg, uint rate)
124{
125 DECLARE_GLOBAL_DATA_PTR;
126
127 volatile immap_t *immr = (immap_t *)CFG_IMMR;
128 volatile uint *bp;
129
130 /* This is good enough to get SMCs running.....
131 */
132 if (brg < 4) {
133 bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
134 }
135 else {
136 bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
137 brg -= 4;
138 }
139 bp += brg;
140 *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
141}
142
143/* This function is used to set high speed synchronous baud rate
144 * clocks.
145 */
146void
147m8560_cpm_fastbrg(uint brg, uint rate, int div16)
148{
149 DECLARE_GLOBAL_DATA_PTR;
150
151 volatile immap_t *immr = (immap_t *)CFG_IMMR;
152 volatile uint *bp;
153
154 /* This is good enough to get SMCs running.....
155 */
156 if (brg < 4) {
157 bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
158 }
159 else {
160 bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
161 brg -= 4;
162 }
163 bp += brg;
164 *bp = (((((BRG_INT_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
165 if (div16)
166 *bp |= CPM_BRG_DIV16;
167}
168
169/* This function is used to set baud rate generators using an external
170 * clock source and 16x oversampling.
171 */
172
173void
174m8560_cpm_extcbrg(uint brg, uint rate, uint extclk, int pinsel)
175{
176 volatile immap_t *immr = (immap_t *)CFG_IMMR;
177 volatile uint *bp;
178
179 if (brg < 4) {
180 bp = (uint *)&(immr->im_cpm.im_cpm_brg1.brgc1);
181 }
182 else {
183 bp = (uint *)&(immr->im_cpm.im_cpm_brg2.brgc5);
184 brg -= 4;
185 }
186 bp += brg;
187 *bp = ((((((extclk/16)+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
188 if (pinsel == 0)
189 *bp |= CPM_BRG_EXTC_CLK3_9;
190 else
191 *bp |= CPM_BRG_EXTC_CLK5_15;
192}
193
194#ifdef CONFIG_POST
195
196void post_word_store (ulong a)
197{
198 volatile ulong *save_addr =
199 (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
200
201 *save_addr = a;
202}
203
204ulong post_word_load (void)
205{
206 volatile ulong *save_addr =
207 (volatile ulong *)(CFG_IMMR + CPM_POST_WORD_ADDR);
208
209 return *save_addr;
210}
211
212#endif /* CONFIG_POST */
213
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -0500214#endif /* CONFIG_CPM2 */