Wolfgang Denk | 70a2047 | 2005-09-25 15:59:01 +0200 | [diff] [blame] | 1 | #!/usr/bin/python |
| 2 | |
| 3 | # (C) Copyright 2004 |
| 4 | # BEC Systems <http://bec-systems.com> |
| 5 | # Cliff Brake <cliff.brake@gmail.com> |
| 6 | |
| 7 | # This program is free software; you can redistribute it and/or |
| 8 | # modify it under the terms of the GNU General Public License as |
| 9 | # published by the Free Software Foundation; either version 2 of |
| 10 | # the License, or (at your option) any later version. |
| 11 | # |
| 12 | # This program is distributed in the hope that it will be useful, |
| 13 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | # GNU General Public License for more details. |
| 16 | # |
| 17 | # You should have received a copy of the GNU General Public License |
| 18 | # along with this program; if not, write to the Free Software |
| 19 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | # MA 02111-1307 USA |
| 21 | |
| 22 | # calculations for PXA255 registers |
| 23 | |
| 24 | class gpio: |
| 25 | dir = '0' |
| 26 | set = '0' |
| 27 | clr = '0' |
| 28 | alt = '0' |
| 29 | desc = '' |
| 30 | |
| 31 | def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): |
| 32 | self.dir = dir |
| 33 | self.set = set |
| 34 | self.clr = clr |
| 35 | self.alt = alt |
| 36 | self.desc = desc |
| 37 | |
| 38 | |
| 39 | # the following is a dictionary of all GPIOs in the system |
| 40 | # the key is the GPIO number |
| 41 | |
| 42 | |
| 43 | pxa255_alt_func = { |
| 44 | 0: ['gpio', 'none', 'none', 'none'], |
| 45 | 1: ['gpio', 'gpio reset', 'none', 'none'], |
| 46 | 2: ['gpio', 'none', 'none', 'none'], |
| 47 | 3: ['gpio', 'none', 'none', 'none'], |
| 48 | 4: ['gpio', 'none', 'none', 'none'], |
| 49 | 5: ['gpio', 'none', 'none', 'none'], |
| 50 | 6: ['gpio', 'MMC clk', 'none', 'none'], |
| 51 | 7: ['gpio', '48MHz clock', 'none', 'none'], |
| 52 | 8: ['gpio', 'MMC CS0', 'none', 'none'], |
| 53 | 9: ['gpio', 'MMC CS1', 'none', 'none'], |
| 54 | 10: ['gpio', 'RTC Clock', 'none', 'none'], |
| 55 | 11: ['gpio', '3.6MHz', 'none', 'none'], |
| 56 | 12: ['gpio', '32KHz', 'none', 'none'], |
| 57 | 13: ['gpio', 'none', 'MBGNT', 'none'], |
| 58 | 14: ['gpio', 'MBREQ', 'none', 'none'], |
| 59 | 15: ['gpio', 'none', 'nCS_1', 'none'], |
| 60 | 16: ['gpio', 'none', 'PWM0', 'none'], |
| 61 | 17: ['gpio', 'none', 'PWM1', 'none'], |
| 62 | 18: ['gpio', 'RDY', 'none', 'none'], |
| 63 | 19: ['gpio', 'DREQ[1]', 'none', 'none'], |
| 64 | 20: ['gpio', 'DREQ[0]', 'none', 'none'], |
| 65 | 21: ['gpio', 'none', 'none', 'none'], |
| 66 | 22: ['gpio', 'none', 'none', 'none'], |
| 67 | 23: ['gpio', 'none', 'SSP SCLK', 'none'], |
| 68 | 24: ['gpio', 'none', 'SSP SFRM', 'none'], |
| 69 | 25: ['gpio', 'none', 'SSP TXD', 'none'], |
| 70 | 26: ['gpio', 'SSP RXD', 'none', 'none'], |
| 71 | 27: ['gpio', 'SSP EXTCLK', 'none', 'none'], |
| 72 | 28: ['gpio', 'AC97 bitclk in, I2S bitclock out', 'I2S bitclock in', 'none'], |
| 73 | 29: ['gpio', 'AC97 SDATA_IN0', 'I2S SDATA_IN', 'none'], |
| 74 | 30: ['gpio', 'I2S SDATA_OUT', 'AC97 SDATA_OUT', 'none'], |
| 75 | 31: ['gpio', 'I2S SYNC', 'AC97 SYNC', 'none'], |
| 76 | 32: ['gpio', 'AC97 SDATA_IN1', 'I2S SYSCLK', 'none'], |
| 77 | 33: ['gpio', 'none', 'nCS_5', 'none'], |
| 78 | 34: ['gpio', 'FF RXD', 'MMC CS0', 'none'], |
| 79 | 35: ['gpio', 'FF CTS', 'none', 'none'], |
| 80 | 36: ['gpio', 'FF DCD', 'none', 'none'], |
| 81 | 37: ['gpio', 'FF DSR', 'none', 'none'], |
| 82 | 38: ['gpio', 'FF RI', 'none', 'none'], |
| 83 | 39: ['gpio', 'MMC CS1', 'FF TXD', 'none'], |
| 84 | 40: ['gpio', 'none', 'FF DTR', 'none'], |
| 85 | 41: ['gpio', 'none', 'FF RTS', 'none'], |
| 86 | 42: ['gpio', 'BT RXD', 'none', 'HW RXD'], |
| 87 | 43: ['gpio', 'none', 'BT TXD', 'HW TXD'], |
| 88 | 44: ['gpio', 'BT CTS', 'none', 'HW CTS'], |
| 89 | 45: ['gpio', 'none', 'BT RTS', 'HW RTS'], |
| 90 | 46: ['gpio', 'ICP_RXD', 'STD RXD', 'none'], |
| 91 | 47: ['gpio', 'STD TXD', 'ICP_TXD', 'none'], |
| 92 | 48: ['gpio', 'HW TXD', 'nPOE', 'none'], |
| 93 | 49: ['gpio', 'HW RXD', 'nPWE', 'none'], |
| 94 | 50: ['gpio', 'HW CTS', 'nPIOR', 'none'], |
| 95 | 51: ['gpio', 'nPIOW', 'HW RTS', 'none'], |
| 96 | 52: ['gpio', 'none', 'nPCE[1]', 'none'], |
| 97 | 53: ['gpio', 'MMC CLK', 'nPCE[2]', 'none'], |
| 98 | 54: ['gpio', 'MMC CLK', 'nPSKSEL', 'none'], |
| 99 | 55: ['gpio', 'none', 'nPREG', 'none'], |
| 100 | 56: ['gpio', 'nPWAIT', 'none', 'none'], |
| 101 | 57: ['gpio', 'nIOIS16', 'none', 'none'], |
| 102 | 58: ['gpio', 'none', 'LDD[0]', 'none'], |
| 103 | 59: ['gpio', 'none', 'LDD[1]', 'none'], |
| 104 | 60: ['gpio', 'none', 'LDD[2]', 'none'], |
| 105 | 61: ['gpio', 'none', 'LDD[3]', 'none'], |
| 106 | 62: ['gpio', 'none', 'LDD[4]', 'none'], |
| 107 | 63: ['gpio', 'none', 'LDD[5]', 'none'], |
| 108 | 64: ['gpio', 'none', 'LDD[6]', 'none'], |
| 109 | 65: ['gpio', 'none', 'LDD[7]', 'none'], |
| 110 | 66: ['gpio', 'MBREQ', 'LDD[8]', 'none'], |
| 111 | 67: ['gpio', 'MMC CS0', 'LDD[9]', 'none'], |
| 112 | 68: ['gpio', 'MMC CS1', 'LDD[10]', 'none'], |
| 113 | 69: ['gpio', 'MMC CLK', 'LDD[11]', 'none'], |
| 114 | 70: ['gpio', 'RTC CLK', 'LDD[12]', 'none'], |
| 115 | 71: ['gpio', '3.6 MHz', 'LDD[13]', 'none'], |
| 116 | 72: ['gpio', '32 KHz', 'LDD[14]', 'none'], |
| 117 | 73: ['gpio', 'MBGNT', 'LDD[15]', 'none'], |
| 118 | 74: ['gpio', 'none', 'LCD_FCLK', 'none'], |
| 119 | 75: ['gpio', 'none', 'LCD_LCLK', 'none'], |
| 120 | 76: ['gpio', 'none', 'LCD_PCLK', 'none'], |
| 121 | 77: ['gpio', 'none', 'LCD_ACBIAS', 'none'], |
| 122 | 78: ['gpio', 'none', 'nCS_2', 'none'], |
| 123 | 79: ['gpio', 'none', 'nCS_3', 'none'], |
| 124 | 80: ['gpio', 'none', 'nCS_4', 'none'], |
| 125 | 81: ['gpio', 'NSSPSCLK', 'none', 'none'], |
| 126 | 82: ['gpio', 'NSSPSFRM', 'none', 'none'], |
| 127 | 83: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], |
| 128 | 84: ['gpio', 'NSSPTXD', 'NSSPRXD', 'none'], |
| 129 | } |
| 130 | |
| 131 | |
| 132 | #def __init__(self, dir=0, set=0, clr=0, alt=0, desc=''): |
| 133 | |
| 134 | gpio_list = [] |
| 135 | |
| 136 | for i in range(0,85): |
| 137 | gpio_list.append(gpio()) |
| 138 | |
| 139 | #chip select GPIOs |
| 140 | gpio_list[18] = gpio(0, 0, 0, 1, 'RDY') |
| 141 | gpio_list[33] = gpio(1, 1, 0, 2, 'CS5#') |
| 142 | gpio_list[80] = gpio(1, 1, 0, 2, 'CS4#') |
| 143 | gpio_list[79] = gpio(1, 1, 0, 2, 'CS3#') |
| 144 | gpio_list[78] = gpio(1, 1, 0, 2, 'CS2#') |
| 145 | gpio_list[15] = gpio(1, 1, 0, 2, 'CS1#') |
| 146 | gpio_list[22] = gpio(0, 0, 0, 0, 'Consumer IR, PCC_S1_IRQ_O#') |
| 147 | gpio_list[21] = gpio(0, 0, 0, 0, 'IRQ_IDE, PFI') |
| 148 | gpio_list[19] = gpio(0, 0, 0, 0, 'XB_DREQ1, PCC_SO_IRQ_O#') |
| 149 | gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') |
| 150 | gpio_list[20] = gpio(0, 0, 0, 0, 'XB_DREQ0') |
| 151 | gpio_list[17] = gpio(0, 0, 0, 0, 'IRQ_AXB') |
| 152 | gpio_list[16] = gpio(1, 0, 0, 2, 'PWM0') |
| 153 | |
| 154 | # PCMCIA stuff |
| 155 | gpio_list[57] = gpio(0, 0, 0, 1, 'PCC_IOIS16#') |
| 156 | gpio_list[56] = gpio(0, 0, 0, 1, 'PCC_WAIT#') |
| 157 | gpio_list[55] = gpio(1, 0, 0, 2, 'PCC_REG#') |
| 158 | gpio_list[54] = gpio(1, 0, 0, 2, 'PCC_SCKSEL') |
| 159 | gpio_list[53] = gpio(1, 1, 0, 2, 'PCC_CE2#') |
| 160 | gpio_list[52] = gpio(1, 1, 0, 2, 'PCC_CE1#') |
| 161 | gpio_list[51] = gpio(1, 1, 0, 1, 'PCC_IOW#') |
| 162 | gpio_list[50] = gpio(1, 1, 0, 2, 'PCC_IOR#') |
| 163 | gpio_list[49] = gpio(1, 1, 0, 2, 'PCC_WE#') |
| 164 | gpio_list[48] = gpio(1, 1, 0, 2, 'PCC_OE#') |
| 165 | |
| 166 | # SSP port |
| 167 | gpio_list[26] = gpio(0, 0, 0, 1, 'SSP_RXD') |
| 168 | gpio_list[25] = gpio(0, 0, 0, 0, 'SSP_TXD') |
| 169 | gpio_list[24] = gpio(1, 0, 1, 2, 'SSP_SFRM') |
| 170 | gpio_list[23] = gpio(1, 0, 1, 2, 'SSP_SCLK') |
| 171 | gpio_list[27] = gpio(0, 0, 0, 0, 'SSP_EXTCLK') |
| 172 | |
| 173 | # audio codec |
| 174 | gpio_list[32] = gpio(0, 0, 0, 0, 'AUD_SDIN1') |
| 175 | gpio_list[31] = gpio(1, 0, 0, 2, 'AC_SYNC') |
| 176 | gpio_list[30] = gpio(1, 0, 0, 2, 'AC_SDOUT') |
| 177 | gpio_list[29] = gpio(0, 0, 0, 1, 'AUD_SDIN0') |
| 178 | gpio_list[28] = gpio(0, 0, 0, 1, 'AC_BITCLK') |
| 179 | |
| 180 | # serial ports |
| 181 | gpio_list[39] = gpio(1, 0, 0, 2, 'FF_TXD') |
| 182 | gpio_list[34] = gpio(0, 0, 0, 1, 'FF_RXD') |
| 183 | gpio_list[41] = gpio(1, 0, 0, 2, 'FF_RTS') |
| 184 | gpio_list[35] = gpio(0, 0, 0, 1, 'FF_CTS') |
| 185 | gpio_list[40] = gpio(1, 0, 0, 2, 'FF_DTR') |
| 186 | gpio_list[37] = gpio(0, 0, 0, 1, 'FF_DSR') |
| 187 | gpio_list[38] = gpio(0, 0, 0, 1, 'FF_RI') |
| 188 | gpio_list[36] = gpio(0, 0, 0, 1, 'FF_DCD') |
| 189 | |
| 190 | gpio_list[43] = gpio(1, 0, 0, 2, 'BT_TXD') |
| 191 | gpio_list[42] = gpio(0, 0, 0, 1, 'BT_RXD') |
| 192 | gpio_list[45] = gpio(1, 0, 0, 2, 'BT_RTS') |
| 193 | gpio_list[44] = gpio(0, 0, 0, 1, 'BT_CTS') |
| 194 | |
| 195 | gpio_list[47] = gpio(1, 0, 0, 1, 'IR_TXD') |
| 196 | gpio_list[46] = gpio(0, 0, 0, 2, 'IR_RXD') |
| 197 | |
| 198 | # misc GPIO signals |
| 199 | gpio_list[14] = gpio(0, 0, 0, 0, 'MBREQ') |
| 200 | gpio_list[13] = gpio(0, 0, 0, 0, 'MBGNT') |
| 201 | gpio_list[12] = gpio(0, 0, 0, 0, 'GPIO_12/32K_CLK') |
| 202 | gpio_list[11] = gpio(0, 0, 0, 0, '3M6_CLK') |
| 203 | gpio_list[10] = gpio(1, 0, 1, 0, 'GPIO_10/RTC_CLK/debug LED') |
| 204 | gpio_list[9] = gpio(0, 0, 0, 0, 'MMC_CD#') |
| 205 | gpio_list[8] = gpio(0, 0, 0, 0, 'PCC_S1_CD#') |
| 206 | gpio_list[7] = gpio(0, 0, 0, 0, 'PCC_S0_CD#') |
| 207 | gpio_list[6] = gpio(1, 0, 0, 1, 'MMC_CLK') |
| 208 | gpio_list[5] = gpio(0, 0, 0, 0, 'IRQ_TOUCH#') |
| 209 | gpio_list[4] = gpio(0, 0, 0, 0, 'IRQ_ETH') |
| 210 | gpio_list[3] = gpio(0, 0, 0, 0, 'MQ_IRQ#') |
| 211 | gpio_list[2] = gpio(0, 0, 0, 0, 'BAT_DATA') |
| 212 | gpio_list[1] = gpio(0, 0, 0, 1, 'USER_RESET#') |
| 213 | gpio_list[0] = gpio(0, 0, 0, 1, 'USER_RESET#') |
| 214 | |
| 215 | # LCD GPIOs |
| 216 | gpio_list[58] = gpio(1, 0, 0, 2, 'LDD0') |
| 217 | gpio_list[59] = gpio(1, 0, 0, 2, 'LDD1') |
| 218 | gpio_list[60] = gpio(1, 0, 0, 2, 'LDD2') |
| 219 | gpio_list[61] = gpio(1, 0, 0, 2, 'LDD3') |
| 220 | gpio_list[62] = gpio(1, 0, 0, 2, 'LDD4') |
| 221 | gpio_list[63] = gpio(1, 0, 0, 2, 'LDD5') |
| 222 | gpio_list[64] = gpio(1, 0, 0, 2, 'LDD6') |
| 223 | gpio_list[65] = gpio(1, 0, 0, 2, 'LDD7') |
| 224 | gpio_list[66] = gpio(1, 0, 0, 2, 'LDD8') |
| 225 | gpio_list[67] = gpio(1, 0, 0, 2, 'LDD9') |
| 226 | gpio_list[68] = gpio(1, 0, 0, 2, 'LDD10') |
| 227 | gpio_list[69] = gpio(1, 0, 0, 2, 'LDD11') |
| 228 | gpio_list[70] = gpio(1, 0, 0, 2, 'LDD12') |
| 229 | gpio_list[71] = gpio(1, 0, 0, 2, 'LDD13') |
| 230 | gpio_list[72] = gpio(1, 0, 0, 2, 'LDD14') |
| 231 | gpio_list[73] = gpio(1, 0, 0, 2, 'LDD15') |
| 232 | gpio_list[74] = gpio(1, 0, 0, 2, 'FCLK') |
| 233 | gpio_list[75] = gpio(1, 0, 0, 2, 'LCLK') |
| 234 | gpio_list[76] = gpio(1, 0, 0, 2, 'PCLK') |
| 235 | gpio_list[77] = gpio(1, 0, 0, 2, 'ACBIAS') |
| 236 | |
| 237 | # calculate registers |
| 238 | pxa_regs = { |
| 239 | 'gpdr0':0, 'gpdr1':0, 'gpdr2':0, |
| 240 | 'gpsr0':0, 'gpsr1':0, 'gpsr2':0, |
| 241 | 'gpcr0':0, 'gpcr1':0, 'gpcr2':0, |
| 242 | 'gafr0_l':0, 'gafr0_u':0, |
| 243 | 'gafr1_l':0, 'gafr1_u':0, |
| 244 | 'gafr2_l':0, 'gafr2_u':0, |
| 245 | } |
| 246 | |
| 247 | # U-boot define names |
| 248 | uboot_reg_names = { |
Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 249 | 'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL', |
| 250 | 'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL', |
| 251 | 'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL', |
| 252 | 'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL', |
| 253 | 'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL', |
| 254 | 'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL', |
Wolfgang Denk | 70a2047 | 2005-09-25 15:59:01 +0200 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | # bit mappings |
| 258 | |
| 259 | bit_mappings = [ |
| 260 | |
| 261 | { 'gpio':(0,32), 'shift':1, 'regs':{'dir':'gpdr0', 'set':'gpsr0', 'clr':'gpcr0'} }, |
| 262 | { 'gpio':(32,64), 'shift':1, 'regs':{'dir':'gpdr1', 'set':'gpsr1', 'clr':'gpcr1'} }, |
| 263 | { 'gpio':(64,85), 'shift':1, 'regs':{'dir':'gpdr2', 'set':'gpsr2', 'clr':'gpcr2'} }, |
| 264 | { 'gpio':(0,16), 'shift':2, 'regs':{'alt':'gafr0_l'} }, |
| 265 | { 'gpio':(16,32), 'shift':2, 'regs':{'alt':'gafr0_u'} }, |
| 266 | { 'gpio':(32,48), 'shift':2, 'regs':{'alt':'gafr1_l'} }, |
| 267 | { 'gpio':(48,64), 'shift':2, 'regs':{'alt':'gafr1_u'} }, |
| 268 | { 'gpio':(64,80), 'shift':2, 'regs':{'alt':'gafr2_l'} }, |
| 269 | { 'gpio':(80,85), 'shift':2, 'regs':{'alt':'gafr2_u'} }, |
| 270 | |
| 271 | ] |
| 272 | |
| 273 | def stuff_bits(bit_mapping, gpio_list): |
| 274 | gpios = range( bit_mapping['gpio'][0], bit_mapping['gpio'][1]) |
| 275 | |
| 276 | for gpio in gpios: |
| 277 | for reg in bit_mapping['regs'].keys(): |
| 278 | value = eval( 'gpio_list[gpio].%s' % (reg) ) |
| 279 | if ( value ): |
| 280 | # we have a high bit |
| 281 | bit_shift = (gpio - bit_mapping['gpio'][0]) * bit_mapping['shift'] |
| 282 | bit = value << (bit_shift) |
| 283 | pxa_regs[bit_mapping['regs'][reg]] |= bit |
| 284 | |
| 285 | for i in bit_mappings: |
| 286 | stuff_bits(i, gpio_list) |
| 287 | |
| 288 | # now print out all regs |
| 289 | registers = pxa_regs.keys() |
| 290 | registers.sort() |
| 291 | for reg in registers: |
| 292 | print '%s: 0x%x' % (reg, pxa_regs[reg]) |
| 293 | |
| 294 | # print define to past right into U-Boot source code |
| 295 | |
| 296 | print |
| 297 | print |
| 298 | |
| 299 | for reg in registers: |
| 300 | print '#define %s 0x%x' % (uboot_reg_names[reg], pxa_regs[reg]) |
| 301 | |
| 302 | # print all GPIOS |
| 303 | print |
| 304 | print |
| 305 | |
| 306 | for i in range(len(gpio_list)): |
| 307 | gpio_i = gpio_list[i] |
| 308 | alt_func_desc = pxa255_alt_func[i][gpio_i.alt] |
| 309 | print 'GPIO: %i, dir=%i, set=%i, clr=%i, alt=%s, desc=%s' % (i, gpio_i.dir, gpio_i.set, gpio_i.clr, alt_func_desc, gpio_i.desc) |
| 310 | |
| 311 | |