blob: 284b2482712c07888b204a4e345161d4f20fa13d [file] [log] [blame]
Wenyou Yang9e5935c2016-07-20 17:55:12 +08001/*
2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk-uclass.h>
10#include <dm/device.h>
11
12DECLARE_GLOBAL_DATA_PTR;
13
14static ulong at91_master_clk_get_rate(struct clk *clk)
15{
16 return gd->arch.mck_rate_hz;
17}
18
19static struct clk_ops at91_master_clk_ops = {
20 .get_rate = at91_master_clk_get_rate,
21};
22
23static const struct udevice_id at91_master_clk_match[] = {
24 { .compatible = "atmel,at91sam9x5-clk-master" },
25 {}
26};
27
28U_BOOT_DRIVER(at91_master_clk) = {
29 .name = "at91-master-clk",
30 .id = UCLASS_CLK,
31 .of_match = at91_master_clk_match,
32 .ops = &at91_master_clk_ops,
33};