blob: cee3c0cb0a63ab96595ec58fe1eae11d5b4e1ba7 [file] [log] [blame]
Stefan Roese4c835a62018-09-05 15:12:35 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Stefan Roese <sr@denx.de>
4 */
5
6#include <common.h>
7#include <dm.h>
Simon Glass9b4a2052019-12-28 10:45:05 -07008#include <init.h>
Stefan Roese4c835a62018-09-05 15:12:35 +02009#include <ram.h>
Stefan Roese4ff942b2018-10-09 08:59:10 +020010#include <wdt.h>
Stefan Roese4c835a62018-09-05 15:12:35 +020011#include <asm/io.h>
12#include <linux/io.h>
13#include <linux/sizes.h>
14#include "mt76xx.h"
15
16#define STR_LEN 6
17
18#ifdef CONFIG_BOOT_ROM
19int mach_cpu_init(void)
20{
21 ddr_calibrate();
22
23 return 0;
24}
25#endif
26
27int dram_init(void)
28{
29 gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_256M);
30
31 return 0;
32}
33
34int print_cpuinfo(void)
35{
36 static const char * const boot_str[] = { "PLL (3-Byte SPI Addr)",
37 "PLL (4-Byte SPI Addr)",
38 "XTAL (3-Byte SPI Addr)",
39 "XTAL (4-Byte SPI Addr)" };
40 const void *blob = gd->fdt_blob;
41 void __iomem *sysc_base;
42 char buf[STR_LEN + 1];
43 fdt_addr_t base;
44 fdt_size_t size;
45 char *str;
46 int node;
47 u32 val;
48
49 /* Get system controller base address */
50 node = fdt_node_offset_by_compatible(blob, -1, "ralink,mt7620a-sysc");
51 if (node < 0)
52 return -FDT_ERR_NOTFOUND;
53
54 base = fdtdec_get_addr_size_auto_noparent(blob, node, "reg",
55 0, &size, true);
56 if (base == FDT_ADDR_T_NONE)
57 return -EINVAL;
58
59 sysc_base = ioremap_nocache(base, size);
60
61 str = (char *)sysc_base + MT76XX_CHIPID_OFFS;
62 snprintf(buf, STR_LEN + 1, "%s", str);
63 val = readl(sysc_base + MT76XX_CHIP_REV_ID_OFFS);
64 printf("CPU: %-*s Rev %ld.%ld - ", STR_LEN, buf,
65 (val & GENMASK(11, 8)) >> 8, val & GENMASK(3, 0));
66
67 val = (readl(sysc_base + MT76XX_SYSCFG0_OFFS) & GENMASK(3, 1)) >> 1;
68 printf("Boot from %s\n", boot_str[val]);
69
70 return 0;
71}
Stefan Roese9814fb22019-05-28 08:11:37 +020072
73int last_stage_init(void)
74{
75 void *src, *dst;
76
77 src = malloc(SZ_64K);
78 dst = malloc(SZ_64K);
79 if (!src || !dst) {
80 printf("Can't allocate buffer for cache cleanup copy!\n");
81 return 0;
82 }
83
84 /*
85 * It has been noticed, that sometimes the d-cache is not in a
86 * "clean-state" when U-Boot is running on MT7688. This was
87 * detected when using the ethernet driver (which uses d-cache)
88 * and a TFTP command does not complete. Copying an area of 64KiB
89 * in DDR at a very late bootup time in U-Boot, directly before
90 * calling into the prompt, seems to fix this issue.
91 */
92 memcpy(dst, src, SZ_64K);
93 free(src);
94 free(dst);
95
96 return 0;
97}