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gerrit.cesnet.cz / github / trini / u-boot / 9b15ce91939d6469dda92eb297b44fa87572629a / . / arch / arm / dts / imx8mm-evk.dts
blob: 2d5d89475b76c333940a57273b26ede4b6cd66a7 [file] [log] [blame]
Peng Fan9b15ce92019-08-27 06:26:08 +0000[diff] [blame^]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6/dts-v1/;
7
8#include "imx8mm.dtsi"
9
10/ {
11 model = "FSL i.MX8MM EVK board";
12 compatible = "fsl,imx8mm-evk", "fsl,imx8mm";
13
14 chosen {
15 stdout-path = &uart2;
16 };
17
18 leds {
19 compatible = "gpio-leds";
20 pinctrl-names = "default";
21 pinctrl-0 = <&pinctrl_gpio_led>;
22
23 status {
24 label = "status";
25 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
26 default-state = "on";
27 };
28 };
29
30 reg_usdhc2_vmmc: regulator-usdhc2 {
31 compatible = "regulator-fixed";
32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
34 regulator-name = "VSD_3V3";
35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
38 enable-active-high;
39 };
40};
41
42&fec1 {
43 pinctrl-names = "default";
44 pinctrl-0 = <&pinctrl_fec1>;
45 phy-mode = "rgmii-id";
46 phy-handle = <&ethphy0>;
47 fsl,magic-packet;
48 status = "okay";
49
50 mdio {
51 #address-cells = <1>;
52 #size-cells = <0>;
53
54 ethphy0: ethernet-phy@0 {
55 compatible = "ethernet-phy-ieee802.3-c22";
56 reg = <0>;
57 at803x,led-act-blind-workaround;
58 at803x,eee-okay;
59 at803x,vddio-1p8v;
60 };
61 };
62};
63
64&uart2 { /* console */
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_uart2>;
67 status = "okay";
68};
69
70&usdhc2 {
71 pinctrl-names = "default", "state_100mhz", "state_200mhz";
72 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
73 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
74 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
75 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
76 bus-width = <4>;
77 vmmc-supply = <&reg_usdhc2_vmmc>;
78 status = "okay";
79};
80
81&usdhc3 {
82 pinctrl-names = "default", "state_100mhz", "state_200mhz";
83 pinctrl-0 = <&pinctrl_usdhc3>;
84 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
85 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
86 bus-width = <8>;
87 non-removable;
88 status = "okay";
89};
90
91&wdog1 {
92 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_wdog>;
94 fsl,ext-reset-output;
95 status = "okay";
96};
97
98&iomuxc {
99 pinctrl-names = "default";
100
101 pinctrl_fec1: fec1grp {
102 fsl,pins = <
103 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
104 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
105 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
106 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
107 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
108 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
109 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
110 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
111 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
112 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
113 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
114 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
115 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
116 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
117 MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
118 >;
119 };
120
121 pinctrl_gpio_led: gpioledgrp {
122 fsl,pins = <
123 MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
124 >;
125 };
126
127 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
128 fsl,pins = <
129 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
130 >;
131 };
132
133 pinctrl_uart2: uart2grp {
134 fsl,pins = <
135 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
136 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
137 >;
138 };
139
140 pinctrl_usdhc2_gpio: usdhc2grpgpio {
141 fsl,pins = <
142 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
143 >;
144 };
145
146 pinctrl_usdhc2: usdhc2grp {
147 fsl,pins = <
148 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
149 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
150 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
151 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
152 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
153 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
154 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
155 >;
156 };
157
158 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
159 fsl,pins = <
160 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
161 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
162 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
163 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
164 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
165 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
166 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
167 >;
168 };
169
170 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
171 fsl,pins = <
172 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
173 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
174 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
175 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
176 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
177 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
178 MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
179 >;
180 };
181
182 pinctrl_usdhc3: usdhc3grp {
183 fsl,pins = <
184 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
185 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
186 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
187 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
188 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
189 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
190 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
191 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
192 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
193 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
194 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
195 >;
196 };
197
198 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
199 fsl,pins = <
200 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
201 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
202 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
203 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
204 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
205 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
206 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
207 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
208 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
209 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
210 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
211 >;
212 };
213
214 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
215 fsl,pins = <
216 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
217 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
218 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
219 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
220 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
221 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
222 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
223 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
224 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
225 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
226 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
227 >;
228 };
229
230 pinctrl_wdog: wdoggrp {
231 fsl,pins = <
232 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
233 >;
234 };
235};