blob: 400e9dd5e24902bc8ce8bdf2cdecbd9fc8dcc855 [file] [log] [blame]
Kumar Galac916d7c2011-04-13 08:37:44 -05001/*
2 * Copyright 2009-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Kumar Galac916d7c2011-04-13 08:37:44 -05006 */
7#include <common.h>
8#include <malloc.h>
9#include <asm/io.h>
10#include <asm/errno.h>
11
12#include "fm.h"
13#include "../../qe/qe.h" /* For struct qe_firmware */
14
Timur Tabif2717b42011-11-22 09:21:25 -060015#ifdef CONFIG_SYS_QE_FMAN_FW_IN_NAND
Kumar Galac916d7c2011-04-13 08:37:44 -050016#include <nand.h>
17#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
18#include <spi_flash.h>
Timur Tabif2717b42011-11-22 09:21:25 -060019#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
Kumar Galac916d7c2011-04-13 08:37:44 -050020#include <mmc.h>
21#endif
22
23struct fm_muram muram[CONFIG_SYS_NUM_FMAN];
24
25u32 fm_muram_base(int fm_idx)
26{
27 return muram[fm_idx].base;
28}
29
30u32 fm_muram_alloc(int fm_idx, u32 size, u32 align)
31{
32 u32 ret;
33 u32 align_mask, off;
34 u32 save;
35
36 align_mask = align - 1;
37 save = muram[fm_idx].alloc;
38
39 off = save & align_mask;
40 if (off != 0)
41 muram[fm_idx].alloc += (align - off);
42 off = size & align_mask;
43 if (off != 0)
44 size += (align - off);
45 if ((muram[fm_idx].alloc + size) >= muram[fm_idx].top) {
46 muram[fm_idx].alloc = save;
47 printf("%s: run out of ram.\n", __func__);
48 }
49
50 ret = muram[fm_idx].alloc;
51 muram[fm_idx].alloc += size;
52 memset((void *)ret, 0, size);
53
54 return ret;
55}
56
57static void fm_init_muram(int fm_idx, void *reg)
58{
59 u32 base = (u32)reg;
60
61 muram[fm_idx].base = base;
62 muram[fm_idx].size = CONFIG_SYS_FM_MURAM_SIZE;
63 muram[fm_idx].alloc = base + FM_MURAM_RES_SIZE;
64 muram[fm_idx].top = base + CONFIG_SYS_FM_MURAM_SIZE;
65}
66
67/*
68 * fm_upload_ucode - Fman microcode upload worker function
69 *
70 * This function does the actual uploading of an Fman microcode
71 * to an Fman.
72 */
73static void fm_upload_ucode(int fm_idx, struct fm_imem *imem,
74 u32 *ucode, unsigned int size)
75{
76 unsigned int i;
77 unsigned int timeout = 1000000;
78
79 /* enable address auto increase */
80 out_be32(&imem->iadd, IRAM_IADD_AIE);
81 /* write microcode to IRAM */
82 for (i = 0; i < size / 4; i++)
83 out_be32(&imem->idata, ucode[i]);
84
85 /* verify if the writing is over */
86 out_be32(&imem->iadd, 0);
87 while ((in_be32(&imem->idata) != ucode[0]) && --timeout)
88 ;
89 if (!timeout)
90 printf("Fman%u: microcode upload timeout\n", fm_idx + 1);
91
92 /* enable microcode from IRAM */
93 out_be32(&imem->iready, IRAM_READY);
94}
95
96/*
97 * Upload an Fman firmware
98 *
99 * This function is similar to qe_upload_firmware(), exception that it uploads
100 * a microcode to the Fman instead of the QE.
101 *
102 * Because the process for uploading a microcode to the Fman is similar for
103 * that of the QE, the QE firmware binary format is used for Fman microcode.
104 * It should be possible to unify these two functions, but for now we keep them
105 * separate.
106 */
107static int fman_upload_firmware(int fm_idx,
108 struct fm_imem *fm_imem,
109 const struct qe_firmware *firmware)
110{
111 unsigned int i;
112 u32 crc;
113 size_t calc_size = sizeof(struct qe_firmware);
114 size_t length;
115 const struct qe_header *hdr;
116
117 if (!firmware) {
118 printf("Fman%u: Invalid address for firmware\n", fm_idx + 1);
119 return -EINVAL;
120 }
121
122 hdr = &firmware->header;
123 length = be32_to_cpu(hdr->length);
124
125 /* Check the magic */
126 if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
127 (hdr->magic[2] != 'F')) {
128 printf("Fman%u: Data at %p is not a firmware\n", fm_idx + 1,
129 firmware);
130 return -EPERM;
131 }
132
133 /* Check the version */
134 if (hdr->version != 1) {
135 printf("Fman%u: Unsupported firmware version %u\n", fm_idx + 1,
136 hdr->version);
137 return -EPERM;
138 }
139
140 /* Validate some of the fields */
141 if ((firmware->count != 1)) {
142 printf("Fman%u: Invalid data in firmware header\n", fm_idx + 1);
143 return -EINVAL;
144 }
145
146 /* Validate the length and check if there's a CRC */
147 calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
148
149 for (i = 0; i < firmware->count; i++)
150 /*
151 * For situations where the second RISC uses the same microcode
152 * as the first, the 'code_offset' and 'count' fields will be
153 * zero, so it's okay to add those.
154 */
155 calc_size += sizeof(u32) *
156 be32_to_cpu(firmware->microcode[i].count);
157
158 /* Validate the length */
159 if (length != calc_size + sizeof(u32)) {
160 printf("Fman%u: Invalid length in firmware header\n",
161 fm_idx + 1);
162 return -EPERM;
163 }
164
165 /*
166 * Validate the CRC. We would normally call crc32_no_comp(), but that
167 * function isn't available unless you turn on JFFS support.
168 */
169 crc = be32_to_cpu(*(u32 *)((void *)firmware + calc_size));
170 if (crc != (crc32(-1, (const void *)firmware, calc_size) ^ -1)) {
171 printf("Fman%u: Firmware CRC is invalid\n", fm_idx + 1);
172 return -EIO;
173 }
174
175 /* Loop through each microcode. */
176 for (i = 0; i < firmware->count; i++) {
177 const struct qe_microcode *ucode = &firmware->microcode[i];
178
179 /* Upload a microcode if it's present */
180 if (ucode->code_offset) {
181 u32 ucode_size;
182 u32 *code;
183 printf("Fman%u: Uploading microcode version %u.%u.%u\n",
184 fm_idx + 1, ucode->major, ucode->minor,
185 ucode->revision);
186 code = (void *)firmware + ucode->code_offset;
187 ucode_size = sizeof(u32) * ucode->count;
188 fm_upload_ucode(fm_idx, fm_imem, code, ucode_size);
189 }
190 }
191
192 return 0;
193}
194
195static u32 fm_assign_risc(int port_id)
196{
197 u32 risc_sel, val;
198 risc_sel = (port_id & 0x1) ? FMFPPRC_RISC2 : FMFPPRC_RISC1;
199 val = (port_id << FMFPPRC_PORTID_SHIFT) & FMFPPRC_PORTID_MASK;
200 val |= ((risc_sel << FMFPPRC_ORA_SHIFT) | risc_sel);
201
202 return val;
203}
204
205static void fm_init_fpm(struct fm_fpm *fpm)
206{
207 int i, port_id;
208 u32 val;
209
210 setbits_be32(&fpm->fmfpee, FMFPEE_EHM | FMFPEE_UEC |
211 FMFPEE_CER | FMFPEE_DER);
212
213 /* IM mode, each even port ID to RISC#1, each odd port ID to RISC#2 */
214
215 /* offline/parser port */
216 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
217 port_id = OH_PORT_ID_BASE + i;
218 val = fm_assign_risc(port_id);
219 out_be32(&fpm->fpmprc, val);
220 }
221 /* Rx 1G port */
222 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
223 port_id = RX_PORT_1G_BASE + i;
224 val = fm_assign_risc(port_id);
225 out_be32(&fpm->fpmprc, val);
226 }
227 /* Tx 1G port */
228 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
229 port_id = TX_PORT_1G_BASE + i;
230 val = fm_assign_risc(port_id);
231 out_be32(&fpm->fpmprc, val);
232 }
233 /* Rx 10G port */
234 port_id = RX_PORT_10G_BASE;
235 val = fm_assign_risc(port_id);
236 out_be32(&fpm->fpmprc, val);
237 /* Tx 10G port */
238 port_id = TX_PORT_10G_BASE;
239 val = fm_assign_risc(port_id);
240 out_be32(&fpm->fpmprc, val);
241
242 /* disable the dispatch limit in IM case */
243 out_be32(&fpm->fpmflc, FMFP_FLC_DISP_LIM_NONE);
244 /* clear events */
245 out_be32(&fpm->fmfpee, FMFPEE_CLEAR_EVENT);
246
247 /* clear risc events */
248 for (i = 0; i < 4; i++)
249 out_be32(&fpm->fpmcev[i], 0xffffffff);
250
251 /* clear error */
252 out_be32(&fpm->fpmrcr, FMFP_RCR_MDEC | FMFP_RCR_IDEC);
253}
254
255static int fm_init_bmi(int fm_idx, struct fm_bmi_common *bmi)
256{
257 int blk, i, port_id;
258 u32 val, offset, base;
259
260 /* alloc free buffer pool in MURAM */
261 base = fm_muram_alloc(fm_idx, FM_FREE_POOL_SIZE, FM_FREE_POOL_ALIGN);
262 if (!base) {
263 printf("%s: no muram for free buffer pool\n", __func__);
264 return -ENOMEM;
265 }
266 offset = base - fm_muram_base(fm_idx);
267
268 /* Need 128KB total free buffer pool size */
269 val = offset / 256;
270 blk = FM_FREE_POOL_SIZE / 256;
271 /* in IM, we must not begin from offset 0 in MURAM */
272 val |= ((blk - 1) << FMBM_CFG1_FBPS_SHIFT);
273 out_be32(&bmi->fmbm_cfg1, val);
274
275 /* disable all BMI interrupt */
276 out_be32(&bmi->fmbm_ier, FMBM_IER_DISABLE_ALL);
277
278 /* clear all events */
279 out_be32(&bmi->fmbm_ievr, FMBM_IEVR_CLEAR_ALL);
280
281 /*
282 * set port parameters - FMBM_PP_x
283 * max tasks 10G Rx/Tx=12, 1G Rx/Tx 4, others is 1
284 * max dma 10G Rx/Tx=3, others is 1
285 * set port FIFO size - FMBM_PFS_x
286 * 4KB for all Rx and Tx ports
287 */
288 /* offline/parser port */
289 for (i = 0; i < MAX_NUM_OH_PORT; i++) {
290 port_id = OH_PORT_ID_BASE + i - 1;
291 /* max tasks=1, max dma=1, no extra */
292 out_be32(&bmi->fmbm_pp[port_id], 0);
293 /* port FIFO size - 256 bytes, no extra */
294 out_be32(&bmi->fmbm_pfs[port_id], 0);
295 }
296 /* Rx 1G port */
297 for (i = 0; i < MAX_NUM_RX_PORT_1G; i++) {
298 port_id = RX_PORT_1G_BASE + i - 1;
299 /* max tasks=4, max dma=1, no extra */
300 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
301 /* FIFO size - 4KB, no extra */
302 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
303 }
304 /* Tx 1G port FIFO size - 4KB, no extra */
305 for (i = 0; i < MAX_NUM_TX_PORT_1G; i++) {
306 port_id = TX_PORT_1G_BASE + i - 1;
307 /* max tasks=4, max dma=1, no extra */
308 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(4));
309 /* FIFO size - 4KB, no extra */
310 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
311 }
312 /* Rx 10G port */
313 port_id = RX_PORT_10G_BASE - 1;
314 /* max tasks=12, max dma=3, no extra */
315 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
316 /* FIFO size - 4KB, no extra */
317 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
318
319 /* Tx 10G port */
320 port_id = TX_PORT_10G_BASE - 1;
321 /* max tasks=12, max dma=3, no extra */
322 out_be32(&bmi->fmbm_pp[port_id], FMBM_PP_MXT(12) | FMBM_PP_MXD(3));
323 /* FIFO size - 4KB, no extra */
324 out_be32(&bmi->fmbm_pfs[port_id], FMBM_PFS_IFSZ(0xf));
325
326 /* initialize internal buffers data base (linked list) */
327 out_be32(&bmi->fmbm_init, FMBM_INIT_START);
328
329 return 0;
330}
331
332static void fm_init_qmi(struct fm_qmi_common *qmi)
333{
334 /* disable enqueue and dequeue of QMI */
335 clrbits_be32(&qmi->fmqm_gc, FMQM_GC_ENQ_EN | FMQM_GC_DEQ_EN);
336
337 /* disable all error interrupts */
338 out_be32(&qmi->fmqm_eien, FMQM_EIEN_DISABLE_ALL);
339 /* clear all error events */
340 out_be32(&qmi->fmqm_eie, FMQM_EIE_CLEAR_ALL);
341
342 /* disable all interrupts */
343 out_be32(&qmi->fmqm_ien, FMQM_IEN_DISABLE_ALL);
344 /* clear all interrupts */
345 out_be32(&qmi->fmqm_ie, FMQM_IE_CLEAR_ALL);
346}
347
348/* Init common part of FM, index is fm num# like fm as above */
349int fm_init_common(int index, struct ccsr_fman *reg)
350{
351 int rc;
Timur Tabif2717b42011-11-22 09:21:25 -0600352#if defined(CONFIG_SYS_QE_FMAN_FW_IN_NOR)
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800353 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
Timur Tabif2717b42011-11-22 09:21:25 -0600354#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_NAND)
355 size_t fw_length = CONFIG_SYS_QE_FMAN_FW_LENGTH;
356 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
Kumar Galac916d7c2011-04-13 08:37:44 -0500357
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800358 rc = nand_read(&nand_info[0], (loff_t)CONFIG_SYS_FMAN_FW_ADDR,
Kumar Galac916d7c2011-04-13 08:37:44 -0500359 &fw_length, (u_char *)addr);
360 if (rc == -EUCLEAN) {
361 printf("NAND read of FMAN firmware at offset 0x%x failed %d\n",
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800362 CONFIG_SYS_FMAN_FW_ADDR, rc);
Kumar Galac916d7c2011-04-13 08:37:44 -0500363 }
364#elif defined(CONFIG_SYS_QE_FW_IN_SPIFLASH)
365 struct spi_flash *ucode_flash;
Timur Tabif2717b42011-11-22 09:21:25 -0600366 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
Kumar Galac916d7c2011-04-13 08:37:44 -0500367 int ret = 0;
368
369 ucode_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
370 CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
371 if (!ucode_flash)
372 printf("SF: probe for ucode failed\n");
373 else {
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800374 ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR,
Timur Tabif2717b42011-11-22 09:21:25 -0600375 CONFIG_SYS_QE_FMAN_FW_LENGTH, addr);
Kumar Galac916d7c2011-04-13 08:37:44 -0500376 if (ret)
377 printf("SF: read for ucode failed\n");
378 spi_flash_free(ucode_flash);
379 }
Timur Tabif2717b42011-11-22 09:21:25 -0600380#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_MMC)
Kumar Galac916d7c2011-04-13 08:37:44 -0500381 int dev = CONFIG_SYS_MMC_ENV_DEV;
Timur Tabif2717b42011-11-22 09:21:25 -0600382 void *addr = malloc(CONFIG_SYS_QE_FMAN_FW_LENGTH);
383 u32 cnt = CONFIG_SYS_QE_FMAN_FW_LENGTH / 512;
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800384 u32 blk = CONFIG_SYS_FMAN_FW_ADDR / 512;
Kumar Galac916d7c2011-04-13 08:37:44 -0500385 struct mmc *mmc = find_mmc_device(CONFIG_SYS_MMC_ENV_DEV);
386
387 if (!mmc)
388 printf("\nMMC cannot find device for ucode\n");
389 else {
390 printf("\nMMC read: dev # %u, block # %u, count %u ...\n",
391 dev, blk, cnt);
392 mmc_init(mmc);
Kumar Gala9ccfed22011-11-09 10:03:55 -0600393 (void)mmc->block_dev.block_read(dev, blk, cnt, addr);
Kumar Galac916d7c2011-04-13 08:37:44 -0500394 /* flush cache after read */
395 flush_cache((ulong)addr, cnt * 512);
396 }
Liu Gang292dc6c2012-03-08 00:33:18 +0000397#elif defined(CONFIG_SYS_QE_FMAN_FW_IN_REMOTE)
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800398 void *addr = (void *)CONFIG_SYS_FMAN_FW_ADDR;
York Sun7adefb52013-06-25 11:37:40 -0700399#else
400 void *addr = NULL;
Kumar Galac916d7c2011-04-13 08:37:44 -0500401#endif
402
403 /* Upload the Fman microcode if it's present */
404 rc = fman_upload_firmware(index, &reg->fm_imem, addr);
405 if (rc)
406 return rc;
Simon Glass978226d2013-02-24 17:33:24 +0000407 setenv_addr("fman_ucode", addr);
Kumar Galac916d7c2011-04-13 08:37:44 -0500408
409 fm_init_muram(index, &reg->muram);
410 fm_init_qmi(&reg->fm_qmi_common);
411 fm_init_fpm(&reg->fm_fpm);
412
413 /* clear DMA status */
414 setbits_be32(&reg->fm_dma.fmdmsr, FMDMSR_CLEAR_ALL);
415
416 /* set DMA mode */
417 setbits_be32(&reg->fm_dma.fmdmmr, FMDMMR_SBER);
418
419 return fm_init_bmi(index, &reg->fm_bmi_common);
420}