blob: bc7e3bd17cbedd9c27a73a2d6dbcde802d7fc216 [file] [log] [blame]
wdenkba56f622004-02-06 23:19:44 +00001/*
2 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23
24#include <common.h>
25#include <asm/processor.h>
26#include <spd_sdram.h>
27#include <i2c.h>
28
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
30
wdenkba56f622004-02-06 23:19:44 +000031#define BOOT_SMALL_FLASH 32 /* 00100000 */
32#define FLASH_ONBD_N 2 /* 00000010 */
33#define FLASH_SRAM_SEL 1 /* 00000001 */
34
35long int fixed_sdram (void);
36
wdenk3c74e322004-02-22 23:46:08 +000037int board_early_init_f(void)
wdenkba56f622004-02-06 23:19:44 +000038{
39 unsigned long sdrreg;
40 /* TBS: Setup the GPIO access for the user LEDs */
41 mfsdr(sdr_pfc0, sdrreg);
42 mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
43 out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
44 LED0_OFF();
45 LED1_OFF();
46 LED2_OFF();
47 LED3_OFF();
48
49 /*--------------------------------------------------------------------
50 * Setup the external bus controller/chip selects
51 *-------------------------------------------------------------------*/
52
53 /* set the bus controller */
54 mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */
55 mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
wdenk3c74e322004-02-22 23:46:08 +000056 mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */
57 mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */
wdenkba56f622004-02-06 23:19:44 +000058
59 /*--------------------------------------------------------------------
60 * Setup the interrupt controller polarities, triggers, etc.
61 *-------------------------------------------------------------------*/
62 mtdcr (uic0sr, 0xffffffff); /* clear all */
63 mtdcr (uic0er, 0x00000000); /* disable all */
64 mtdcr (uic0cr, 0x00000003); /* SMI & UIC1 crit are critical */
65 mtdcr (uic0pr, 0xfffffe00); /* per ref-board manual */
66 mtdcr (uic0tr, 0x01c00000); /* per ref-board manual */
67 mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
68 mtdcr (uic0sr, 0xffffffff); /* clear all */
69
70 mtdcr (uic1sr, 0xffffffff); /* clear all */
71 mtdcr (uic1er, 0x00000000); /* disable all */
72 mtdcr (uic1cr, 0x00000000); /* all non-critical */
73 mtdcr (uic1pr, 0xffffc0ff); /* per ref-board manual */
74 mtdcr (uic1tr, 0x00ff8000); /* per ref-board manual */
75 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
76 mtdcr (uic1sr, 0xffffffff); /* clear all */
77
78 mtdcr (uic2sr, 0xffffffff); /* clear all */
79 mtdcr (uic2er, 0x00000000); /* disable all */
80 mtdcr (uic2cr, 0x00000000); /* all non-critical */
81 mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
82 mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
83 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
84 mtdcr (uic2sr, 0xffffffff); /* clear all */
85
86 mtdcr (uicb0sr, 0xfc000000); /* clear all */
87 mtdcr (uicb0er, 0x00000000); /* disable all */
88 mtdcr (uicb0cr, 0x00000000); /* all non-critical */
89 mtdcr (uicb0pr, 0xfc000000); /* */
90 mtdcr (uicb0tr, 0x00000000); /* */
91 mtdcr (uicb0vr, 0x00000001); /* */
92
93 LED0_ON();
94
95
96 return 0;
97}
98
99int checkboard (void)
100{
wdenkba56f622004-02-06 23:19:44 +0000101 printf ("Board: XES XPedite1000 440GX\n");
wdenkba56f622004-02-06 23:19:44 +0000102
103 return (0);
104}
105
106
Becky Bruce9973e3c2008-06-09 16:03:40 -0500107phys_size_t initdram (int board_type)
wdenkba56f622004-02-06 23:19:44 +0000108{
109 long dram_size = 0;
110
111#if defined(CONFIG_SPD_EEPROM)
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200112 dram_size = spd_sdram ();
wdenkba56f622004-02-06 23:19:44 +0000113#else
114 dram_size = fixed_sdram ();
115#endif
116 return dram_size;
117}
118
119
120#if defined(CFG_DRAM_TEST)
121int testdram (void)
122{
123 uint *pstart = (uint *) 0x00000000;
124 uint *pend = (uint *) 0x08000000;
125 uint *p;
126
127 for (p = pstart; p < pend; p++)
128 *p = 0xaaaaaaaa;
129
130 for (p = pstart; p < pend; p++) {
131 if (*p != 0xaaaaaaaa) {
132 printf ("SDRAM test fails at: %08x\n", (uint) p);
133 return 1;
134 }
135 }
136
137 for (p = pstart; p < pend; p++)
138 *p = 0x55555555;
139
140 for (p = pstart; p < pend; p++) {
141 if (*p != 0x55555555) {
142 printf ("SDRAM test fails at: %08x\n", (uint) p);
143 return 1;
144 }
145 }
146 return 0;
147}
148#endif
149
150#if !defined(CONFIG_SPD_EEPROM)
151/*************************************************************************
152 * fixed sdram init -- doesn't use serial presence detect.
153 *
154 * Assumes: 128 MB, non-ECC, non-registered
155 * PLB @ 133 MHz
156 *
157 ************************************************************************/
158long int fixed_sdram (void)
159{
160 uint reg;
161
162 /*--------------------------------------------------------------------
163 * Setup some default
164 *------------------------------------------------------------------*/
165 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */
166 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
167 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
168 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
169 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
170
171 /*--------------------------------------------------------------------
172 * Setup for board-specific specific mem
173 *------------------------------------------------------------------*/
174 /*
175 * Following for CAS Latency = 2.5 @ 133 MHz PLB
176 */
177 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
178 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
179 /* RA=10 RD=3 */
180 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
181 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
182 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
183 udelay (400); /* Delay 200 usecs (min) */
184
185 /*--------------------------------------------------------------------
186 * Enable the controller, then wait for DCEN to complete
187 *------------------------------------------------------------------*/
188 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
189 for (;;) {
190 mfsdram (mem_mcsts, reg);
191 if (reg & 0x80000000)
192 break;
193 }
194
195 return (128 * 1024 * 1024); /* 128 MB */
196}
197#endif /* !defined(CONFIG_SPD_EEPROM) */
198
199
200/*************************************************************************
201 * pci_pre_init
202 *
203 * This routine is called just prior to registering the hose and gives
204 * the board the opportunity to check things. Returning a value of zero
205 * indicates that things are bad & PCI initialization should be aborted.
206 *
207 * Different boards may wish to customize the pci controller structure
208 * (add regions, override default access routines, etc) or perform
209 * certain pre-initialization actions.
210 *
211 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200212#if defined(CONFIG_PCI)
wdenkba56f622004-02-06 23:19:44 +0000213int pci_pre_init(struct pci_controller * hose )
214{
215 unsigned long strap;
wdenk3c74e322004-02-22 23:46:08 +0000216 /* See if we're supposed to setup the pci */
217 mfsdr(sdr_sdstp1, strap);
218 if ((strap & 0x00010000) == 0) {
219 return (0);
wdenkba56f622004-02-06 23:19:44 +0000220 }
221
wdenk3c74e322004-02-22 23:46:08 +0000222#if defined(CFG_PCI_FORCE_PCI_CONV)
223 /* Setup System Device Register PCIX0_XCR */
224 mfsdr(sdr_xcr, strap);
225 strap &= 0x0f000000;
226 mtsdr(sdr_xcr, strap);
227#endif
wdenkba56f622004-02-06 23:19:44 +0000228 return 1;
229}
Stefan Roese466fff12007-06-25 15:57:39 +0200230#endif /* defined(CONFIG_PCI) */
wdenkba56f622004-02-06 23:19:44 +0000231
232/*************************************************************************
233 * pci_target_init
234 *
235 * The bootstrap configuration provides default settings for the pci
236 * inbound map (PIM). But the bootstrap config choices are limited and
237 * may not be sufficient for a given board.
238 *
239 ************************************************************************/
240#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
241void pci_target_init(struct pci_controller * hose )
242{
wdenkba56f622004-02-06 23:19:44 +0000243 /*--------------------------------------------------------------------------+
244 * Disable everything
245 *--------------------------------------------------------------------------*/
246 out32r( PCIX0_PIM0SA, 0 ); /* disable */
247 out32r( PCIX0_PIM1SA, 0 ); /* disable */
248 out32r( PCIX0_PIM2SA, 0 ); /* disable */
249 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
250
251 /*--------------------------------------------------------------------------+
252 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
253 * options to not support sizes such as 128/256 MB.
254 *--------------------------------------------------------------------------*/
255 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
256 out32r( PCIX0_PIM0LAH, 0 );
257 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
258
259 out32r( PCIX0_BAR0, 0 );
260
261 /*--------------------------------------------------------------------------+
262 * Program the board's subsystem id/vendor id
263 *--------------------------------------------------------------------------*/
264 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
265 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
266
267 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
268}
269#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
270
271
272/*************************************************************************
273 * is_pci_host
274 *
275 * This routine is called to determine if a pci scan should be
276 * performed. With various hardware environments (especially cPCI and
277 * PPMC) it's insufficient to depend on the state of the arbiter enable
278 * bit in the strap register, or generic host/adapter assumptions.
279 *
280 * Rather than hard-code a bad assumption in the general 440 code, the
281 * 440 pci code requires the board to decide at runtime.
282 *
283 * Return 0 for adapter mode, non-zero for host (monarch) mode.
284 *
285 *
286 ************************************************************************/
287#if defined(CONFIG_PCI)
288int is_pci_host(struct pci_controller *hose)
289{
wdenk3c74e322004-02-22 23:46:08 +0000290 return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0);
wdenkba56f622004-02-06 23:19:44 +0000291}
292#endif /* defined(CONFIG_PCI) */
293
294#ifdef CONFIG_POST
295/*
296 * Returns 1 if keys pressed to start the power-on long-running tests
297 * Called from board_init_f().
298 */
299int post_hotkeys_pressed(void)
300{
301
302 return (ctrlc());
303}
304
305void post_word_store (ulong a)
306{
307 volatile ulong *save_addr =
308 (volatile ulong *)(CFG_POST_WORD_ADDR);
309
310 *save_addr = a;
311}
312
313ulong post_word_load (void)
314{
315 volatile ulong *save_addr =
316 (volatile ulong *)(CFG_POST_WORD_ADDR);
317
318 return *save_addr;
319}
320#endif
321
322/*-----------------------------------------------------------------------------
323 * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM
324 *-----------------------------------------------------------------------------
325 */
326static int enetaddr_num = 0;
327void board_get_enetaddr (uchar * enet)
328{
329 int i;
330 unsigned char buff[0x100], *cp;
331
332 /* Initialize I2C */
333 i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
334
335 /* Read 256 bytes in EEPROM */
336 i2c_read (0x50, 0, 1, buff, 0x100);
337
338 if (enetaddr_num == 0) {
339 cp = &buff[0xF4];
340 enetaddr_num = 1;
341 }
342 else
343 cp = &buff[0xFA];
344
345 for (i = 0; i < 6; i++,cp++)
346 enet[i] = *cp;
347
348 printf ("MAC address = %02x:%02x:%02x:%02x:%02x:%02x\n",
349 enet[0], enet[1], enet[2], enet[3], enet[4], enet[5]);
350
351}