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wdenk945af8d2003-07-16 21:53:01 +00001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
wdenke35745b2004-04-18 23:32:11 +00005 * (C) Copyright 2004
6 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
7 *
wdenk945af8d2003-07-16 21:53:01 +00008 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#include <common.h>
28#include <mpc5xxx.h>
wdenk96e48cf2003-08-05 18:22:44 +000029#include <pci.h>
Rafal Jaworowskib66a9382006-03-29 13:17:09 +020030#include <asm/processor.h>
Grant Likelycf2817a2007-09-06 09:46:23 -060031#include <libfdt.h>
Stefan Roesee59581c2006-11-28 17:55:49 +010032
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010033#if defined(CONFIG_LITE5200B)
34#include "mt46v32m16.h"
wdenke35745b2004-04-18 23:32:11 +000035#else
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010036# if defined(CONFIG_MPC5200_DDR)
37# include "mt46v16m16-75.h"
38# else
wdenke35745b2004-04-18 23:32:11 +000039#include "mt48lc16m16a2-75.h"
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +010040# endif
wdenke35745b2004-04-18 23:32:11 +000041#endif
Domen Puncerd3832e82007-04-16 14:00:13 +020042
43#ifdef CONFIG_LITE5200B_PM
44/* u-boot part of low-power mode implementation */
45#define SAVED_ADDR (*(void **)0x00000000)
46#define PSC2_4 0x02
47
48void lite5200b_wakeup(void)
49{
50 unsigned char wakeup_pin;
51 void (*linux_wakeup)(void);
52
53 /* check PSC2_4, if it's down "QT" is signaling we have a wakeup
54 * from low power mode */
55 *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4;
56 __asm__ volatile ("sync");
57
58 wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I;
59 if (wakeup_pin & PSC2_4)
60 return;
61
62 /* acknowledge to "QT"
63 * by holding pin at 1 for 10 uS */
64 *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4;
65 __asm__ volatile ("sync");
66 *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4;
67 __asm__ volatile ("sync");
68 udelay(10);
69
70 /* put ram out of self-refresh */
71 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */
72 __asm__ volatile ("sync");
73 *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */
74 __asm__ volatile ("sync");
75 *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */
76 __asm__ volatile ("sync");
77 udelay(10); /* wait a bit */
78
79 /* jump back to linux kernel code */
80 linux_wakeup = SAVED_ADDR;
81 printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n",
82 linux_wakeup);
83 linux_wakeup();
84}
85#else
86#define lite5200b_wakeup()
87#endif
88
wdenkd94f92c2003-08-28 09:41:22 +000089#ifndef CFG_RAMBOOT
wdenke0ac62d2003-08-17 18:55:18 +000090static void sdram_start (int hi_addr)
91{
92 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
93
wdenkb2001f22003-12-20 22:45:10 +000094 /* unlock mode register */
wdenke35745b2004-04-18 23:32:11 +000095 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
96 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +000097
wdenkb2001f22003-12-20 22:45:10 +000098 /* precharge all banks */
wdenke35745b2004-04-18 23:32:11 +000099 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
100 __asm__ volatile ("sync");
101
102#if SDRAM_DDR
wdenkb2001f22003-12-20 22:45:10 +0000103 /* set mode register: extended mode */
wdenke35745b2004-04-18 23:32:11 +0000104 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
105 __asm__ volatile ("sync");
106
wdenkb2001f22003-12-20 22:45:10 +0000107 /* set mode register: reset DLL */
wdenke35745b2004-04-18 23:32:11 +0000108 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
109 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000110#endif
wdenke35745b2004-04-18 23:32:11 +0000111
112 /* precharge all banks */
113 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
114 __asm__ volatile ("sync");
115
wdenkf8d813e2004-03-02 14:05:39 +0000116 /* auto refresh */
wdenke35745b2004-04-18 23:32:11 +0000117 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
118 __asm__ volatile ("sync");
119
wdenke0ac62d2003-08-17 18:55:18 +0000120 /* set mode register */
wdenke35745b2004-04-18 23:32:11 +0000121 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
122 __asm__ volatile ("sync");
wdenk5cf91d62004-04-23 20:32:05 +0000123
wdenke0ac62d2003-08-17 18:55:18 +0000124 /* normal operation */
wdenke35745b2004-04-18 23:32:11 +0000125 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
126 __asm__ volatile ("sync");
wdenke0ac62d2003-08-17 18:55:18 +0000127}
wdenkd94f92c2003-08-28 09:41:22 +0000128#endif
wdenke0ac62d2003-08-17 18:55:18 +0000129
wdenke35745b2004-04-18 23:32:11 +0000130/*
131 * ATTENTION: Although partially referenced initdram does NOT make real use
132 * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
133 * is something else than 0x00000000.
134 */
135
136#if defined(CONFIG_MPC5200)
Becky Bruce9973e3c2008-06-09 16:03:40 -0500137phys_size_t initdram (int board_type)
wdenk945af8d2003-07-16 21:53:01 +0000138{
wdenkd94f92c2003-08-28 09:41:22 +0000139 ulong dramsize = 0;
wdenkb2001f22003-12-20 22:45:10 +0000140 ulong dramsize2 = 0;
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200141 uint svr, pvr;
142
wdenk945af8d2003-07-16 21:53:01 +0000143#ifndef CFG_RAMBOOT
wdenkd94f92c2003-08-28 09:41:22 +0000144 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000145
wdenke35745b2004-04-18 23:32:11 +0000146 /* setup SDRAM chip selects */
wdenke0ac62d2003-08-17 18:55:18 +0000147 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
148 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
wdenke35745b2004-04-18 23:32:11 +0000149 __asm__ volatile ("sync");
wdenk945af8d2003-07-16 21:53:01 +0000150
wdenkb2001f22003-12-20 22:45:10 +0000151 /* setup config registers */
wdenke35745b2004-04-18 23:32:11 +0000152 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
153 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
154 __asm__ volatile ("sync");
wdenkd4ca31c2004-01-02 14:00:00 +0000155
wdenke35745b2004-04-18 23:32:11 +0000156#if SDRAM_DDR
157 /* set tap delay */
158 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
159 __asm__ volatile ("sync");
wdenkb2001f22003-12-20 22:45:10 +0000160#endif
wdenk945af8d2003-07-16 21:53:01 +0000161
wdenke35745b2004-04-18 23:32:11 +0000162 /* find RAM size using SDRAM CS0 only */
wdenke0ac62d2003-08-17 18:55:18 +0000163 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200164 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000165 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200166 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke0ac62d2003-08-17 18:55:18 +0000167 if (test1 > test2) {
168 sdram_start(0);
169 dramsize = test1;
170 } else {
171 dramsize = test2;
172 }
wdenke35745b2004-04-18 23:32:11 +0000173
174 /* memory smaller than 1MB is impossible */
175 if (dramsize < (1 << 20)) {
176 dramsize = 0;
177 }
wdenk5cf91d62004-04-23 20:32:05 +0000178
wdenke35745b2004-04-18 23:32:11 +0000179 /* set SDRAM CS0 size according to the amount of RAM found */
180 if (dramsize > 0) {
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
182 } else {
183 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
184 }
185
wdenke35745b2004-04-18 23:32:11 +0000186 /* let SDRAM CS1 start right after CS0 */
wdenkb2001f22003-12-20 22:45:10 +0000187 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
wdenke35745b2004-04-18 23:32:11 +0000188
189 /* find RAM size using SDRAM CS1 only */
wdenk07cc0992005-05-05 00:04:14 +0000190 if (!dramsize)
wdenka6310922005-04-21 21:10:22 +0000191 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200192 test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000193 if (!dramsize) {
194 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200195 test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
wdenka6310922005-04-21 21:10:22 +0000196 }
wdenkb2001f22003-12-20 22:45:10 +0000197 if (test1 > test2) {
198 sdram_start(0);
199 dramsize2 = test1;
200 } else {
201 dramsize2 = test2;
202 }
wdenk5cf91d62004-04-23 20:32:05 +0000203
wdenke35745b2004-04-18 23:32:11 +0000204 /* memory smaller than 1MB is impossible */
205 if (dramsize2 < (1 << 20)) {
206 dramsize2 = 0;
207 }
wdenk5cf91d62004-04-23 20:32:05 +0000208
wdenke35745b2004-04-18 23:32:11 +0000209 /* set SDRAM CS1 size according to the amount of RAM found */
210 if (dramsize2 > 0) {
211 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
212 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
213 } else {
214 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
215 }
wdenke0ac62d2003-08-17 18:55:18 +0000216
wdenke35745b2004-04-18 23:32:11 +0000217#else /* CFG_RAMBOOT */
218
219 /* retrieve size of memory connected to SDRAM CS0 */
220 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
221 if (dramsize >= 0x13) {
222 dramsize = (1 << (dramsize - 0x13)) << 20;
223 } else {
224 dramsize = 0;
225 }
226
227 /* retrieve size of memory connected to SDRAM CS1 */
228 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
229 if (dramsize2 >= 0x13) {
230 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
231 } else {
232 dramsize2 = 0;
233 }
234
wdenkd94f92c2003-08-28 09:41:22 +0000235#endif /* CFG_RAMBOOT */
wdenkb2001f22003-12-20 22:45:10 +0000236
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200237 /*
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200238 * On MPC5200B we need to set the special configuration delay in the
239 * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200240 * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
241 *
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200242 * "The SDelay should be written to a value of 0x00000004. It is
243 * required to account for changes caused by normal wafer processing
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200244 * parameters."
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200245 */
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200246 svr = get_svr();
247 pvr = get_pvr();
Wolfgang Denkcf48eb92006-04-16 10:51:58 +0200248 if ((SVR_MJREV(svr) >= 2) &&
Rafal Jaworowskib66a9382006-03-29 13:17:09 +0200249 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
250
251 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
252 __asm__ volatile ("sync");
253 }
254
Domen Puncerd3832e82007-04-16 14:00:13 +0200255 lite5200b_wakeup();
256
wdenke35745b2004-04-18 23:32:11 +0000257 return dramsize + dramsize2;
258}
259
260#elif defined(CONFIG_MGT5100)
261
Becky Bruce9973e3c2008-06-09 16:03:40 -0500262phys_size_t initdram (int board_type)
wdenke35745b2004-04-18 23:32:11 +0000263{
264 ulong dramsize = 0;
265#ifndef CFG_RAMBOOT
266 ulong test1, test2;
wdenk5cf91d62004-04-23 20:32:05 +0000267
wdenke35745b2004-04-18 23:32:11 +0000268 /* setup and enable SDRAM chip selects */
269 *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
270 *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
271 *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
272 __asm__ volatile ("sync");
273
274 /* setup config registers */
275 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
276 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
277
278 /* address select register */
279 *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
280 __asm__ volatile ("sync");
281
282 /* find RAM size */
283 sdram_start(0);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200284 test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000285 sdram_start(1);
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200286 test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
wdenke35745b2004-04-18 23:32:11 +0000287 if (test1 > test2) {
288 sdram_start(0);
289 dramsize = test1;
290 } else {
291 dramsize = test2;
292 }
293
294 /* set SDRAM end address according to size */
295 *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
wdenk5cf91d62004-04-23 20:32:05 +0000296
wdenke35745b2004-04-18 23:32:11 +0000297#else /* CFG_RAMBOOT */
298
299 /* Retrieve amount of SDRAM available */
300 dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
301
302#endif /* CFG_RAMBOOT */
303
wdenke0ac62d2003-08-17 18:55:18 +0000304 return dramsize;
wdenk945af8d2003-07-16 21:53:01 +0000305}
306
wdenke35745b2004-04-18 23:32:11 +0000307#else
308#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
309#endif
310
wdenk945af8d2003-07-16 21:53:01 +0000311int checkboard (void)
312{
Wolfgang Denk09e4b0c2006-03-17 11:42:53 +0100313#if defined (CONFIG_LITE5200B)
314 puts ("Board: Freescale Lite5200B\n");
315#elif defined(CONFIG_MPC5200)
wdenk945af8d2003-07-16 21:53:01 +0000316 puts ("Board: Motorola MPC5200 (IceCube)\n");
317#elif defined(CONFIG_MGT5100)
318 puts ("Board: Motorola MGT5100 (IceCube)\n");
319#endif
320 return 0;
321}
322
323void flash_preinit(void)
324{
325 /*
326 * Now, when we are in RAM, enable flash write
327 * access for detection process.
328 * Note that CS_BOOT cannot be cleared when
329 * executing in flash.
330 */
331#if defined(CONFIG_MGT5100)
332 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
333 *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
334#endif
335 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
336}
wdenk96e48cf2003-08-05 18:22:44 +0000337
wdenk7152b1d2003-09-05 23:19:14 +0000338void flash_afterinit(ulong size)
339{
340 if (size == 0x800000) { /* adjust mapping */
wdenk42d1f032003-10-15 23:53:47 +0000341 *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
wdenk7152b1d2003-09-05 23:19:14 +0000342 START_REG(CFG_BOOTCS_START | size);
wdenk42d1f032003-10-15 23:53:47 +0000343 *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
wdenk7152b1d2003-09-05 23:19:14 +0000344 STOP_REG(CFG_BOOTCS_START | size, size);
345 }
346}
347
wdenk96e48cf2003-08-05 18:22:44 +0000348#ifdef CONFIG_PCI
349static struct pci_controller hose;
350
351extern void pci_mpc5xxx_init(struct pci_controller *);
352
353void pci_init_board(void)
354{
355 pci_mpc5xxx_init(&hose);
356}
357#endif
wdenkc3f9d492004-03-14 00:59:59 +0000358
Jon Loeliger77a31852007-07-10 10:39:10 -0500359#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
wdenkc3f9d492004-03-14 00:59:59 +0000360
wdenkc3f9d492004-03-14 00:59:59 +0000361void init_ide_reset (void)
362{
wdenk4d13cba2004-03-14 14:09:05 +0000363 debug ("init_ide_reset\n");
wdenk42dfe7a2004-03-14 22:25:36 +0000364
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100365 /* Configure PSC1_4 as GPIO output for ATA reset */
wdenkc3f9d492004-03-14 00:59:59 +0000366 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
wdenk4d13cba2004-03-14 14:09:05 +0000367 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000368 /* Deassert reset */
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100369 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000370}
371
372void ide_set_reset (int idereset)
373{
wdenk4d13cba2004-03-14 14:09:05 +0000374 debug ("ide_reset(%d)\n", idereset);
375
wdenkc3f9d492004-03-14 00:59:59 +0000376 if (idereset) {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100377 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
wdenk64f70be2004-09-28 20:34:50 +0000378 /* Make a delay. MPC5200 spec says 25 usec min */
379 udelay(500000);
wdenkc3f9d492004-03-14 00:59:59 +0000380 } else {
Bartlomiej Siekadae80f32006-11-01 01:38:16 +0100381 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
wdenkc3f9d492004-03-14 00:59:59 +0000382 }
383}
Jon Loeliger77a31852007-07-10 10:39:10 -0500384#endif
Stefan Roesee59581c2006-11-28 17:55:49 +0100385
Grant Likelycf2817a2007-09-06 09:46:23 -0600386#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
Stefan Roesee59581c2006-11-28 17:55:49 +0100387void
388ft_board_setup(void *blob, bd_t *bd)
389{
390 ft_cpu_setup(blob, bd);
391}
392#endif