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wdenka6c7ad22002-12-03 21:28:10 +00001/*
2 * (C) Copyright 2002
3 * Stäubli Faverges - <www.staubli.com>
4 * Pierre AUBERT p.aubert@staubli.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24/* Video support for the ECCX daughter board */
25
26
27#include <common.h>
28#include <config.h>
29
30#ifdef CONFIG_VIDEO_SED13806
31#include <sed13806.h>
32
33
34
35/* Screen configurations: the initialization of the SD13806 depends on
36 screen and on display mode. We handle only 8bpp and 16 bpp modes */
37
38/* ECCX board is supplied with a NEC NL6448BC20 screen */
39#ifdef CONFIG_NEC_NL6448BC20
40#define DISPLAY_WIDTH 640
41#define DISPLAY_HEIGHT 480
42
43#ifdef CONFIG_VIDEO_SED13806_8BPP
44static const S1D_REGS init_regs [] =
45{
46 {0x0001,0x00}, // Miscellaneous Register
47 {0x01FC,0x00}, // Display Mode Register
48 {0x0004,0x1b}, // General IO Pins Configuration Register 0
49 {0x0005,0x00}, // General IO Pins Configuration Register 1
50 {0x0008,0xe5}, // General IO Pins Control Register 0
51 {0x0009,0x1f}, // General IO Pins Control Register 1
52 {0x0010,0x02}, // Memory Clock Configuration Register
53 {0x0014,0x10}, // LCD Pixel Clock Configuration Register
54 {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
55 {0x001C,0x02}, // MediaPlug Clock Configuration Register
56 {0x001E,0x01}, // CPU To Memory Wait State Select Register
57 {0x0021,0x04}, // DRAM Refresh Rate Register
58 {0x002A,0x00}, // DRAM Timings Control Register 0
59 {0x002B,0x01}, // DRAM Timings Control Register 1
60 {0x0020,0x80}, // Memory Configuration Register
61 {0x0030,0x25}, // Panel Type Register
62 {0x0031,0x00}, // MOD Rate Register
63 {0x0032,0x4F}, // LCD Horizontal Display Width Register
64 {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
65 {0x0035,0x01}, // TFT FPLINE Start Position Register
66 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
67 {0x0038,0xDF}, // LCD Vertical Display Height Register 0
68 {0x0039,0x01}, // LCD Vertical Display Height Register 1
69 {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
70 {0x003B,0x00}, // TFT FPFRAME Start Position Register
71 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
72 {0x0040,0x03}, // LCD Display Mode Register
73 {0x0041,0x02}, // LCD Miscellaneous Register
74 {0x0042,0x00}, // LCD Display Start Address Register 0
75 {0x0043,0x00}, // LCD Display Start Address Register 1
76 {0x0044,0x00}, // LCD Display Start Address Register 2
77 {0x0046,0x40}, // LCD Memory Address Offset Register 0
78 {0x0047,0x01}, // LCD Memory Address Offset Register 1
79 {0x0048,0x00}, // LCD Pixel Panning Register
80 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
81 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
82 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
83 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
84 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
85 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
86 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
87 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
88 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
89 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
90 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
91 {0x005B,0x00}, // TV Output Control Register
92 {0x0060,0x03}, // CRT/TV Display Mode Register
93 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
94 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
95 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
96 {0x0066,0x40}, // CRT/TV Memory Address Offset Register 0
97 {0x0067,0x01}, // CRT/TV Memory Address Offset Register 1
98 {0x0068,0x00}, // CRT/TV Pixel Panning Register
99 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
100 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
101 {0x0070,0x00}, // LCD Ink/Cursor Control Register
102 {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
103 {0x0072,0x00}, // LCD Cursor X Position Register 0
104 {0x0073,0x00}, // LCD Cursor X Position Register 1
105 {0x0074,0x00}, // LCD Cursor Y Position Register 0
106 {0x0075,0x00}, // LCD Cursor Y Position Register 1
107 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
108 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
109 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
110 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
111 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
112 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
113 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
114 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
115 {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
116 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
117 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
118 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
119 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
120 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
121 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
122 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
123 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
124 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
125 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
126 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
127 {0x0100,0x00}, // BitBlt Control Register 0
128 {0x0101,0x00}, // BitBlt Control Register 1
129 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
130 {0x0103,0x00}, // BitBlt Operation Register
131 {0x0104,0x00}, // BitBlt Source Start Address Register 0
132 {0x0105,0x00}, // BitBlt Source Start Address Register 1
133 {0x0106,0x00}, // BitBlt Source Start Address Register 2
134 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
135 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
136 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
137 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
138 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
139 {0x0110,0x00}, // BitBlt Width Register 0
140 {0x0111,0x00}, // BitBlt Width Register 1
141 {0x0112,0x00}, // BitBlt Height Register 0
142 {0x0113,0x00}, // BitBlt Height Register 1
143 {0x0114,0x00}, // BitBlt Background Color Register 0
144 {0x0115,0x00}, // BitBlt Background Color Register 1
145 {0x0118,0x00}, // BitBlt Foreground Color Register 0
146 {0x0119,0x00}, // BitBlt Foreground Color Register 1
147 {0x01E0,0x00}, // Look-Up Table Mode Register
148 {0x01E2,0x00}, // Look-Up Table Address Register
149 {0x01E4,0x00}, // Look-Up Table Data Register
150 {0x01F0,0x10}, // Power Save Configuration Register
151 {0x01F1,0x00}, // Power Save Status Register
152 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
153 {0x01FC,0x01}, // Display Mode Register
154 {0, 0}
155};
156#endif /* CONFIG_VIDEO_SED13806_8BPP */
157
158#ifdef CONFIG_VIDEO_SED13806_16BPP
159
160static const S1D_REGS init_regs [] =
161{
162 {0x0001,0x00}, // Miscellaneous Register
163 {0x01FC,0x00}, // Display Mode Register
164 {0x0004,0x1b}, // General IO Pins Configuration Register 0
165 {0x0005,0x00}, // General IO Pins Configuration Register 1
166 {0x0008,0xe5}, // General IO Pins Control Register 0
167 {0x0009,0x1f}, // General IO Pins Control Register 1
168 {0x0010,0x02}, // Memory Clock Configuration Register
169 {0x0014,0x10}, // LCD Pixel Clock Configuration Register
170 {0x0018,0x02}, // CRT/TV Pixel Clock Configuration Register
171 {0x001C,0x02}, // MediaPlug Clock Configuration Register
172 {0x001E,0x01}, // CPU To Memory Wait State Select Register
173 {0x0021,0x04}, // DRAM Refresh Rate Register
174 {0x002A,0x00}, // DRAM Timings Control Register 0
175 {0x002B,0x01}, // DRAM Timings Control Register 1
176 {0x0020,0x80}, // Memory Configuration Register
177 {0x0030,0x25}, // Panel Type Register
178 {0x0031,0x00}, // MOD Rate Register
179 {0x0032,0x4F}, // LCD Horizontal Display Width Register
180 {0x0034,0x13}, // LCD Horizontal Non-Display Period Register
181 {0x0035,0x01}, // TFT FPLINE Start Position Register
182 {0x0036,0x0B}, // TFT FPLINE Pulse Width Register
183 {0x0038,0xDF}, // LCD Vertical Display Height Register 0
184 {0x0039,0x01}, // LCD Vertical Display Height Register 1
185 {0x003A,0x2C}, // LCD Vertical Non-Display Period Register
186 {0x003B,0x00}, // TFT FPFRAME Start Position Register
187 {0x003C,0x01}, // TFT FPFRAME Pulse Width Register
188 {0x0040,0x05}, // LCD Display Mode Register
189 {0x0041,0x02}, // LCD Miscellaneous Register
190 {0x0042,0x00}, // LCD Display Start Address Register 0
191 {0x0043,0x00}, // LCD Display Start Address Register 1
192 {0x0044,0x00}, // LCD Display Start Address Register 2
193 {0x0046,0x80}, // LCD Memory Address Offset Register 0
194 {0x0047,0x02}, // LCD Memory Address Offset Register 1
195 {0x0048,0x00}, // LCD Pixel Panning Register
196 {0x004A,0x00}, // LCD Display FIFO High Threshold Control Register
197 {0x004B,0x00}, // LCD Display FIFO Low Threshold Control Register
198 {0x0050,0x4F}, // CRT/TV Horizontal Display Width Register
199 {0x0052,0x13}, // CRT/TV Horizontal Non-Display Period Register
200 {0x0053,0x01}, // CRT/TV HRTC Start Position Register
201 {0x0054,0x0B}, // CRT/TV HRTC Pulse Width Register
202 {0x0056,0xDF}, // CRT/TV Vertical Display Height Register 0
203 {0x0057,0x01}, // CRT/TV Vertical Display Height Register 1
204 {0x0058,0x2B}, // CRT/TV Vertical Non-Display Period Register
205 {0x0059,0x09}, // CRT/TV VRTC Start Position Register
206 {0x005A,0x01}, // CRT/TV VRTC Pulse Width Register
207 {0x005B,0x00}, // TV Output Control Register
208 {0x0060,0x05}, // CRT/TV Display Mode Register
209 {0x0062,0x00}, // CRT/TV Display Start Address Register 0
210 {0x0063,0x00}, // CRT/TV Display Start Address Register 1
211 {0x0064,0x00}, // CRT/TV Display Start Address Register 2
212 {0x0066,0x80}, // CRT/TV Memory Address Offset Register 0
213 {0x0067,0x02}, // CRT/TV Memory Address Offset Register 1
214 {0x0068,0x00}, // CRT/TV Pixel Panning Register
215 {0x006A,0x00}, // CRT/TV Display FIFO High Threshold Control Register
216 {0x006B,0x00}, // CRT/TV Display FIFO Low Threshold Control Register
217 {0x0070,0x00}, // LCD Ink/Cursor Control Register
218 {0x0071,0x00}, // LCD Ink/Cursor Start Address Register
219 {0x0072,0x00}, // LCD Cursor X Position Register 0
220 {0x0073,0x00}, // LCD Cursor X Position Register 1
221 {0x0074,0x00}, // LCD Cursor Y Position Register 0
222 {0x0075,0x00}, // LCD Cursor Y Position Register 1
223 {0x0076,0x00}, // LCD Ink/Cursor Blue Color 0 Register
224 {0x0077,0x00}, // LCD Ink/Cursor Green Color 0 Register
225 {0x0078,0x00}, // LCD Ink/Cursor Red Color 0 Register
226 {0x007A,0x1F}, // LCD Ink/Cursor Blue Color 1 Register
227 {0x007B,0x3F}, // LCD Ink/Cursor Green Color 1 Register
228 {0x007C,0x1F}, // LCD Ink/Cursor Red Color 1 Register
229 {0x007E,0x00}, // LCD Ink/Cursor FIFO Threshold Register
230 {0x0080,0x00}, // CRT/TV Ink/Cursor Control Register
231 {0x0081,0x00}, // CRT/TV Ink/Cursor Start Address Register
232 {0x0082,0x00}, // CRT/TV Cursor X Position Register 0
233 {0x0083,0x00}, // CRT/TV Cursor X Position Register 1
234 {0x0084,0x00}, // CRT/TV Cursor Y Position Register 0
235 {0x0085,0x00}, // CRT/TV Cursor Y Position Register 1
236 {0x0086,0x00}, // CRT/TV Ink/Cursor Blue Color 0 Register
237 {0x0087,0x00}, // CRT/TV Ink/Cursor Green Color 0 Register
238 {0x0088,0x00}, // CRT/TV Ink/Cursor Red Color 0 Register
239 {0x008A,0x1F}, // CRT/TV Ink/Cursor Blue Color 1 Register
240 {0x008B,0x3F}, // CRT/TV Ink/Cursor Green Color 1 Register
241 {0x008C,0x1F}, // CRT/TV Ink/Cursor Red Color 1 Register
242 {0x008E,0x00}, // CRT/TV Ink/Cursor FIFO Threshold Register
243 {0x0100,0x00}, // BitBlt Control Register 0
244 {0x0101,0x00}, // BitBlt Control Register 1
245 {0x0102,0x00}, // BitBlt ROP Code/Color Expansion Register
246 {0x0103,0x00}, // BitBlt Operation Register
247 {0x0104,0x00}, // BitBlt Source Start Address Register 0
248 {0x0105,0x00}, // BitBlt Source Start Address Register 1
249 {0x0106,0x00}, // BitBlt Source Start Address Register 2
250 {0x0108,0x00}, // BitBlt Destination Start Address Register 0
251 {0x0109,0x00}, // BitBlt Destination Start Address Register 1
252 {0x010A,0x00}, // BitBlt Destination Start Address Register 2
253 {0x010C,0x00}, // BitBlt Memory Address Offset Register 0
254 {0x010D,0x00}, // BitBlt Memory Address Offset Register 1
255 {0x0110,0x00}, // BitBlt Width Register 0
256 {0x0111,0x00}, // BitBlt Width Register 1
257 {0x0112,0x00}, // BitBlt Height Register 0
258 {0x0113,0x00}, // BitBlt Height Register 1
259 {0x0114,0x00}, // BitBlt Background Color Register 0
260 {0x0115,0x00}, // BitBlt Background Color Register 1
261 {0x0118,0x00}, // BitBlt Foreground Color Register 0
262 {0x0119,0x00}, // BitBlt Foreground Color Register 1
263 {0x01E0,0x01}, // Look-Up Table Mode Register
264 {0x01E2,0x00}, // Look-Up Table Address Register
265 {0x01E4,0x00}, // Look-Up Table Data Register
266 {0x01F0,0x10}, // Power Save Configuration Register
267 {0x01F1,0x00}, // Power Save Status Register
268 {0x01F4,0x00}, // CPU-to-Memory Access Watchdog Timer Register
269 {0x01FC,0x01}, // Display Mode Register
270 {0, 0}
271};
272
273#endif /* CONFIG_VIDEO_SED13806_16BPP */
274#endif /* CONFIG_NEC_NL6448BC20 */
275
276
277
278#ifdef CONFIG_CONSOLE_EXTRA_INFO
279
280/*-----------------------------------------------------------------------------
281 * video_get_info_str -- setup a board string: type, speed, etc.
282 * line_number= location to place info string beside logo
283 * info= buffer for info string
284 *-----------------------------------------------------------------------------
285 */
286void video_get_info_str (int line_number, char *info)
287{
288 if (line_number == 1) {
289 strcpy (info, " RPXClassic board");
290 }
291 else {
292 info [0] = '\0';
293 }
294
295}
296#endif
297
298/*-----------------------------------------------------------------------------
299 * board_video_init -- init de l'EPSON, config du CS
300 *-----------------------------------------------------------------------------
301 */
302unsigned int board_video_init (void)
303{
304 volatile immap_t *immap = (immap_t *)CFG_IMMR;
305 volatile memctl8xx_t *memctl = &immap->im_memctl;
306
307 /* Program ECCX registers */
308 *(ECCX_CSR12) |= ECCX_860;
309 *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
310 *(ECCX_CSR8) |= ECCX_ENEPSON;
311
312 memctl->memc_or2 = SED13806_OR;
313 memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;
314
315 return (SED13806_REG_ADDR);
316}
317
318/*-----------------------------------------------------------------------------
319 * board_validate_screen --
320 *-----------------------------------------------------------------------------
321 */
322void board_validate_screen (unsigned int base)
323{
324 /* Activate the panel bias power */
325 *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
326}
327/*-----------------------------------------------------------------------------
328 * board_get_regs --
329 *-----------------------------------------------------------------------------
330 */
331const S1D_REGS *board_get_regs (void)
332{
333 return (init_regs);
334}
335/*-----------------------------------------------------------------------------
336 * board_get_width --
337 *-----------------------------------------------------------------------------
338 */
339int board_get_width (void)
340{
341 return (DISPLAY_WIDTH);
342}
343
344/*-----------------------------------------------------------------------------
345 * board_get_height --
346 *-----------------------------------------------------------------------------
347 */
348int board_get_height (void)
349{
350 return (DISPLAY_HEIGHT);
351}
352
353#endif /* CONFIG_VIDEO_SED13806 */