blob: 480a59f05bbed6d3d17e0cb68f79d946b39626fa [file] [log] [blame]
Wolfgang Denk265817c2005-09-25 00:53:22 +02001/*
2 * (C) Copyright 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * This file contains the configuration parameters for the dbau1x00 board.
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32#define CONFIG_PB1X00 1
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090033#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
Wolfgang Denk265817c2005-09-25 00:53:22 +020034
35#ifdef CONFIG_PB1000
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090036#define CONFIG_SOC_AU1000 1
Wolfgang Denk265817c2005-09-25 00:53:22 +020037#else
38#ifdef CONFIG_PB1100
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090039#define CONFIG_SOC_AU1100 1
Wolfgang Denk265817c2005-09-25 00:53:22 +020040#else
41#ifdef CONFIG_PB1500
Shinya Kuribayashi8bde63e2008-06-07 20:51:56 +090042#define CONFIG_SOC_AU1500 1
Wolfgang Denk265817c2005-09-25 00:53:22 +020043#else
44#error "No valid board set"
45#endif
46#endif
47#endif
48
49#define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */
50
51#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
52
53#define CONFIG_BAUDRATE 115200
54
55/* valid baudrates */
56#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
57
58#define CONFIG_TIMESTAMP /* Print image info with timestamp */
59#undef CONFIG_BOOTARGS
60
61#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010062 "addmisc=setenv bootargs ${bootargs} " \
63 "console=ttyS0,${baudrate} " \
Wolfgang Denk265817c2005-09-25 00:53:22 +020064 "panic=1\0" \
65 "bootfile=/vmlinux.img\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010066 "load=tftp 80500000 ${u-boot}\0" \
Wolfgang Denk265817c2005-09-25 00:53:22 +020067 ""
68/* Boot from NFS root */
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069#define CONFIG_BOOTCOMMAND "bootp; setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; bootm"
Wolfgang Denk265817c2005-09-25 00:53:22 +020070
71/*
72 * Miscellaneous configurable options
73 */
74#define CFG_LONGHELP /* undef to save memory */
75#define CFG_PROMPT "Pb1x00 # " /* Monitor Command Prompt */
76#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
77#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
78#define CFG_MAXARGS 16 /* max number of command args*/
79
80#define CFG_MALLOC_LEN 128*1024
81
82#define CFG_BOOTPARAMS_LEN 128*1024
83
Shinya Kuribayashia55d4812008-06-05 22:29:00 +090084#define CFG_MIPS_TIMER_FREQ 396000000
85
86#define CFG_HZ 1000
Wolfgang Denk265817c2005-09-25 00:53:22 +020087
88#define CFG_SDRAM_BASE 0x80000000 /* Cached addr */
89
90#define CFG_LOAD_ADDR 0x81000000 /* default load address */
91
92#define CFG_MEMTEST_START 0x80100000
93#undef CFG_MEMTEST_START
94#define CFG_MEMTEST_START 0x80200000
95#define CFG_MEMTEST_END 0x83800000
96
97/*-----------------------------------------------------------------------
98 * FLASH and environment organization
99 */
100#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
101#define CFG_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
102
103#define PHYS_FLASH_1 0xbec00000 /* Flash Bank #1 */
104#define PHYS_FLASH_2 0xbfc00000 /* Flash Bank #2 */
105
106/* The following #defines are needed to get flash environment right */
107#define CFG_MONITOR_BASE TEXT_BASE
108#define CFG_MONITOR_LEN (192 << 10)
109
110#define CFG_INIT_SP_OFFSET 0x4000000
111
112/* We boot from this flash, selected with dip switch */
113#define CFG_FLASH_BASE PHYS_FLASH_2
114
115/* timeout values are in ticks */
116#define CFG_FLASH_ERASE_TOUT (2 * CFG_HZ) /* Timeout for Flash Erase */
117#define CFG_FLASH_WRITE_TOUT (2 * CFG_HZ) /* Timeout for Flash Write */
118
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200119#define CONFIG_ENV_IS_NOWHERE 1
Wolfgang Denk265817c2005-09-25 00:53:22 +0200120
121/* Address and size of Primary Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200122#define CONFIG_ENV_ADDR 0xB0030000
123#define CONFIG_ENV_SIZE 0x10000
Wolfgang Denk265817c2005-09-25 00:53:22 +0200124
125#define CONFIG_FLASH_16BIT
126
127#define CONFIG_NR_DRAM_BANKS 2
128
129#define CONFIG_NET_MULTI
130
131#define CONFIG_MEMSIZE_IN_BYTES
132
133
134/*---USB -------------------------------------------*/
135#if 0
136#define CONFIG_USB_OHCI
Wolfgang Denk265817c2005-09-25 00:53:22 +0200137#define CONFIG_USB_STORAGE
138#define CONFIG_DOS_PARTITION
Wolfgang Denk265817c2005-09-25 00:53:22 +0200139#endif
140
141/*---ATA PCMCIA ------------------------------------*/
142#if 0
143#define CFG_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
144#define CFG_PCMCIA_MEM_ADDR 0x20000000
145#define CONFIG_PCMCIA_SLOT_A
146
147#define CONFIG_ATAPI 1
148#define CONFIG_MAC_PARTITION 1
149
150/* We run CF in "true ide" mode or a harddrive via pcmcia */
151#define CONFIG_IDE_PCMCIA 1
152
153/* We only support one slot for now */
154#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
155#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
156
157#undef CONFIG_IDE_LED /* LED for ide not supported */
158#undef CONFIG_IDE_RESET /* reset for ide not supported */
159
160#define CFG_ATA_IDE0_OFFSET 0x0000
161
162#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
163
164/* Offset for data I/O */
165#define CFG_ATA_DATA_OFFSET 8
166
167/* Offset for normal register accesses */
168#define CFG_ATA_REG_OFFSET 0
169
170/* Offset for alternate registers */
171#define CFG_ATA_ALT_OFFSET 0x0100
172
173#endif
174/*-----------------------------------------------------------------------
175 * Cache Configuration
176 */
177#define CFG_DCACHE_SIZE 16384
178#define CFG_ICACHE_SIZE 16384
179#define CFG_CACHELINE_SIZE 32
180
Jon Loeliger26a34562007-07-04 22:33:17 -0500181
182/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500183 * BOOTP options
184 */
185#define CONFIG_BOOTP_BOOTFILESIZE
186#define CONFIG_BOOTP_BOOTPATH
187#define CONFIG_BOOTP_GATEWAY
188#define CONFIG_BOOTP_HOSTNAME
189
190
191/*
Jon Loeliger26a34562007-07-04 22:33:17 -0500192 * Command line configuration.
193 */
194#include <config_cmd_default.h>
195
196#define CONFIG_CMD_DHCP
197#define CONFIG_CMD_ELF
198#define CONFIG_CMD_MII
199#define CONFIG_CMD_PING
200
201#undef CONFIG_CMD_ENV
202#undef CONFIG_CMD_FAT
203#undef CONFIG_CMD_FLASH
204#undef CONFIG_CMD_FPGA
205#undef CONFIG_CMD_IDE
206#undef CONFIG_CMD_LOADS
207#undef CONFIG_CMD_RUN
208#undef CONFIG_CMD_LOADB
209#undef CONFIG_CMD_ELF
210#undef CONFIG_CMD_BDI
211#undef CONFIG_CMD_BEDBUG
Wolfgang Denk265817c2005-09-25 00:53:22 +0200212
213#endif /* __CONFIG_H */