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Tapani Utriainen550e3752013-12-04 09:27:33 +01001/*
2 * Configuration settings for the TechNexion TAO-3530 SOM
3 * equipped on Thunder baseboard.
4 *
5 * Edward Lin <linuxfae@technexion.com>
6 * Tapani Utriainen <linuxfae@technexion.com>
7 *
Stefan Roesea9f52492013-12-04 09:27:34 +01008 * Copyright (C) 2013 Stefan Roese <sr@denx.de>
9 *
Tapani Utriainen550e3752013-12-04 09:27:33 +010010 * SPDX-License-Identifier: GPL-2.0+
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16/*
17 * High Level Configuration Options
18 */
Tapani Utriainen550e3752013-12-04 09:27:33 +010019#define CONFIG_OMAP /* in a TI OMAP core */
Tapani Utriainen550e3752013-12-04 09:27:33 +010020
21#define CONFIG_OMAP_GPIO
22#define CONFIG_OMAP_COMMON
Stefan Roese188948e2014-07-09 17:18:11 +020023#define CONFIG_SYS_GENERIC_BOARD
Tapani Utriainen550e3752013-12-04 09:27:33 +010024
25#define MACH_TYPE_OMAP3_TAO3530 2836
26
27#define CONFIG_SDRC /* Has an SDRC controller */
28
29#include <asm/arch/cpu.h> /* get chip and board defs */
Nishanth Menon987ec582015-03-09 17:12:04 -050030#include <asm/arch/omap.h>
Tapani Utriainen550e3752013-12-04 09:27:33 +010031
32/*
33 * Display CPU and Board information
34 */
35#define CONFIG_DISPLAY_CPUINFO
36#define CONFIG_DISPLAY_BOARDINFO
37
38/* Clock Defines */
39#define V_OSCK 26000000 /* Clock output from T2 */
40#define V_SCLK (V_OSCK >> 1)
41
42#define CONFIG_MISC_INIT_R
43
44#define CONFIG_OF_LIBFDT
45
46#define CONFIG_CMDLINE_TAG
47#define CONFIG_SETUP_MEMORY_TAGS
48#define CONFIG_INITRD_TAG
49#define CONFIG_REVISION_TAG
50
51/*
52 * Size of malloc() pool
53 */
54#define CONFIG_SYS_MALLOC_LEN (4 << 20)
55#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
56
57/*
58 * Hardware drivers
59 */
60
61/*
62 * NS16550 Configuration
63 */
64#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
65
66#define CONFIG_SYS_NS16550
67#define CONFIG_SYS_NS16550_SERIAL
68#define CONFIG_SYS_NS16550_REG_SIZE (-4)
69#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
70
71/*
72 * select serial console configuration
73 */
74#define CONFIG_CONS_INDEX 3
75#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
76
77/* allow to overwrite serial and ethaddr */
78#define CONFIG_ENV_OVERWRITE
79#define CONFIG_BAUDRATE 115200
80#define CONFIG_GENERIC_MMC
81#define CONFIG_MMC
82#define CONFIG_OMAP_HSMMC
83#define CONFIG_DOS_PARTITION
84
Stefan Roese36481de2014-02-14 09:47:17 +010085/* GPIO banks */
86#define CONFIG_OMAP3_GPIO_2 /* GPIO32 ..63 is in GPIO bank 2 */
87#define CONFIG_OMAP3_GPIO_3 /* GPIO64 ..95 is in GPIO bank 3 */
88#define CONFIG_OMAP3_GPIO_4 /* GPIO96 ..127 is in GPIO bank 4 */
89#define CONFIG_OMAP3_GPIO_5 /* GPIO128..159 is in GPIO bank 5 */
90#define CONFIG_OMAP3_GPIO_6 /* GPIO160..191 is in GPIO bank 6 */
91
Tapani Utriainen550e3752013-12-04 09:27:33 +010092/* commands to include */
93#include <config_cmd_default.h>
94
95#define CONFIG_CMD_CACHE
96#define CONFIG_CMD_EXT2 /* EXT2 Support */
97#define CONFIG_CMD_FAT /* FAT support */
98#define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
99#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
100#define MTDIDS_DEFAULT "nand0=nand"
101#define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
102 "1920k(u-boot),128k(u-boot-env),"\
103 "4m(kernel),-(fs)"
104
105#define CONFIG_CMD_I2C /* I2C serial bus support */
106#define CONFIG_CMD_MMC /* MMC support */
107#define CONFIG_CMD_NAND /* NAND support */
108#define CONFIG_CMD_DHCP
109#define CONFIG_CMD_PING
110
111#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
112#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
113#undef CONFIG_CMD_IMI /* iminfo */
114#undef CONFIG_CMD_IMLS /* List all found images */
115
116#define CONFIG_SYS_NO_FLASH
117#define CONFIG_SYS_I2C
118#define CONFIG_SYS_I2C_OMAP34XX
119#define CONFIG_SYS_OMAP24_I2C_SPEED 100000
120#define CONFIG_SYS_OMAP24_I2C_SLAVE 1
121#define CONFIG_I2C_MULTI_BUS
122
123/*
124 * TWL4030
125 */
126#define CONFIG_TWL4030_POWER
127#define CONFIG_TWL4030_LED
128
129/*
130 * Board NAND Info.
131 */
132#define CONFIG_SYS_NAND_QUIET_TEST
133#define CONFIG_NAND_OMAP_GPMC
134#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
135 /* to access nand */
136#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
137 /* to access nand at */
138 /* CS0 */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100139
140#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
141 /* devices */
pekon guptab80a6602014-05-06 00:46:19 +0530142#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16
Tapani Utriainen550e3752013-12-04 09:27:33 +0100143/* Environment information */
144#define CONFIG_BOOTDELAY 3
145
146#define CONFIG_EXTRA_ENV_SETTINGS \
147 "loadaddr=0x82000000\0" \
148 "console=ttyO2,115200n8\0" \
149 "mpurate=600\0" \
150 "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \
151 "tv_mode=omapfb.mode=tv:ntsc\0" \
152 "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \
153 "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \
154 "extra_options= \0" \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100155 "mmcdev=0\0" \
156 "mmcroot=/dev/mmcblk0p2 rw\0" \
157 "mmcrootfstype=ext3 rootwait\0" \
158 "nandroot=ubi0:rootfs ubi.mtd=4\0" \
159 "nandrootfstype=ubifs\0" \
160 "mmcargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100161 "mpurate=${mpurate} " \
162 "${video_mode} " \
163 "root=${mmcroot} " \
164 "rootfstype=${mmcrootfstype} " \
165 "${extra_options}\0" \
166 "nandargs=setenv bootargs console=${console} " \
Tapani Utriainen550e3752013-12-04 09:27:33 +0100167 "mpurate=${mpurate} " \
168 "${video_mode} " \
169 "${network_setting} " \
170 "root=${nandroot} " \
171 "rootfstype=${nandrootfstype} "\
172 "${extra_options}\0" \
173 "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
174 "bootscript=echo Running bootscript from mmc ...; " \
175 "source ${loadaddr}\0" \
176 "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
177 "mmcboot=echo Booting from mmc ...; " \
178 "run mmcargs; " \
179 "bootm ${loadaddr}\0" \
180 "nandboot=echo Booting from nand ...; " \
181 "run nandargs; " \
182 "nand read ${loadaddr} 280000 400000; " \
183 "bootm ${loadaddr}\0" \
184
185#define CONFIG_BOOTCOMMAND \
186 "if mmc rescan ${mmcdev}; then " \
187 "if run loadbootscript; then " \
188 "run bootscript; " \
189 "else " \
190 "if run loaduimage; then " \
191 "run mmcboot; " \
192 "else run nandboot; " \
193 "fi; " \
194 "fi; " \
195 "else run nandboot; fi"
196
197/*
198 * Miscellaneous configurable options
199 */
200#define CONFIG_SYS_LONGHELP /* undef to save memory */
201#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
202#define CONFIG_SYS_PROMPT "TAO-3530 # "
203#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
204
205/* turn on command-line edit/hist/auto */
206#define CONFIG_CMDLINE_EDITING
207#define CONFIG_COMMAND_HISTORY
208#define CONFIG_AUTO_COMPLETE
209
210/* Print Buffer Size */
211#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
212 sizeof(CONFIG_SYS_PROMPT) + 16)
213#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
214/* Boot Argument Buffer Size */
215#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
216
217#define CONFIG_SYS_ALT_MEMTEST 1
218#define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */
219 /* defaults */
220#define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */
221#define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */
222
223#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
224 /* load address */
225#define CONFIG_SYS_TEXT_BASE 0x80008000
226
227/*
228 * OMAP3 has 12 GP timers, they can be driven by the system clock
229 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
230 * This rate is divided by a local divisor.
231 */
232#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
233#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
234
235/*
236 * Stack sizes
237 *
238 * The stack sizes are set up in start.S using the settings below
239 */
240#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
241
242/*
243 * Physical Memory Map
244 */
245#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
246#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
247#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
248#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
249
250/*
251 * FLASH and environment organization
252 */
253
254/* **** PISMO SUPPORT *** */
Tapani Utriainen550e3752013-12-04 09:27:33 +0100255#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
pekon gupta222a3112014-07-18 17:59:41 +0530256#define CONFIG_SYS_FLASH_BASE NAND_BASE
Tapani Utriainen550e3752013-12-04 09:27:33 +0100257
258/* Monitor at start of flash */
259#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
260#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
261
262#define CONFIG_ENV_IS_IN_NAND 1
263#define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
264#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
265
266#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10)
267#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
268#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
269
270#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
271#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
272#define CONFIG_SYS_INIT_RAM_SIZE 0x800
273#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
274 CONFIG_SYS_INIT_RAM_SIZE - \
275 GENERATED_GBL_DATA_SIZE)
276
277#define CONFIG_OMAP3_SPI
278
279/*
280 * USB
281 *
282 * Currently only EHCI is enabled, the MUSB OTG controller
283 * is not enabled.
284 */
285
286/* USB EHCI */
287#define CONFIG_CMD_USB
288#define CONFIG_USB_EHCI
289#define CONFIG_USB_EHCI_OMAP
290#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162
291
292#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
293#define CONFIG_USB_HOST_ETHER
294#define CONFIG_USB_ETHER_SMSC95XX
295
296#define CONFIG_USB_ETHER
297#define CONFIG_USB_ETHER_RNDIS
298#define CONFIG_USB_STORAGE
299#define CONGIG_CMD_STORAGE
300
Stefan Roesea9f52492013-12-04 09:27:34 +0100301/* Defines for SPL */
Stefan Roesea9f52492013-12-04 09:27:34 +0100302#define CONFIG_SPL_FRAMEWORK
303#define CONFIG_SPL_NAND_SIMPLE
304
305#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
306#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
Paul Kocialkowskie2ccdf82014-11-08 23:14:55 +0100307#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200308#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Stefan Roesea9f52492013-12-04 09:27:34 +0100309
310#define CONFIG_SPL_BOARD_INIT
311#define CONFIG_SPL_LIBCOMMON_SUPPORT
312#define CONFIG_SPL_LIBDISK_SUPPORT
313#define CONFIG_SPL_I2C_SUPPORT
314#define CONFIG_SPL_LIBGENERIC_SUPPORT
315#define CONFIG_SPL_MMC_SUPPORT
316#define CONFIG_SPL_FAT_SUPPORT
317#define CONFIG_SPL_SERIAL_SUPPORT
318#define CONFIG_SPL_NAND_SUPPORT
319#define CONFIG_SPL_NAND_BASE
320#define CONFIG_SPL_NAND_DRIVERS
321#define CONFIG_SPL_NAND_ECC
322#define CONFIG_SPL_GPIO_SUPPORT
323#define CONFIG_SPL_POWER_SUPPORT
324#define CONFIG_SPL_OMAP3_ID_NAND
325#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
326
327/* NAND boot config */
328#define CONFIG_SYS_NAND_5_ADDR_CYCLE
329#define CONFIG_SYS_NAND_PAGE_COUNT 64
330#define CONFIG_SYS_NAND_PAGE_SIZE 2048
331#define CONFIG_SYS_NAND_OOBSIZE 64
332#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
333#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
334/*
335 * Use the ECC/OOB layout from omap_gpmc.h that matches your chip:
336 * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT
337 */
338#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
339 10, 11, 12, 13 }
340#define CONFIG_SYS_NAND_ECCSIZE 512
341#define CONFIG_SYS_NAND_ECCBYTES 3
342#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
343
344#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
345#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
346
347#define CONFIG_SPL_TEXT_BASE 0x40200800
348#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Stefan Roesea9f52492013-12-04 09:27:34 +0100349
350/*
351 * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the
352 * older x-loader implementations. And move the BSS area so that it
353 * doesn't overlap with TEXT_BASE.
354 */
355#define CONFIG_SYS_TEXT_BASE 0x80008000
356#define CONFIG_SPL_BSS_START_ADDR 0x80100000
357#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
358
359#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
360#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
361
Tapani Utriainen550e3752013-12-04 09:27:33 +0100362#endif /* __CONFIG_H */