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Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21#include <common.h>
Stefan Roesec25dd8f2007-08-23 11:02:37 +020022#include <command.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020023#include <ppc440.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020024#include <asm/processor.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020025#include <asm/gpio.h>
Stefan Roese04e6c382007-07-04 10:06:30 +020026#include <asm/io.h>
Stefan Roeseb765ffb2007-06-15 08:18:01 +020027
28DECLARE_GLOBAL_DATA_PTR;
29
30extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
31
Stefan Roese3ad63872007-08-21 16:27:57 +020032ulong flash_get_size(ulong base, int banknum);
33int misc_init_r_kbd(void);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020034
35int board_early_init_f(void)
36{
37 u32 sdr0_pfc1, sdr0_pfc2;
38 u32 reg;
39
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020040 /* PLB Write pipelining disabled. Denali Core workaround */
41 mtdcr(plb0_acr, 0xDE000000);
42 mtdcr(plb1_acr, 0xDE000000);
Stefan Roeseb765ffb2007-06-15 08:18:01 +020043
44 /*--------------------------------------------------------------------
45 * Setup the interrupt controller polarities, triggers, etc.
46 *-------------------------------------------------------------------*/
47 mtdcr(uic0sr, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
48 mtdcr(uic0er, 0x00000000); /* disable all */
49 mtdcr(uic0cr, 0x00000000); /* we have not critical interrupts at the moment */
Stefan Roeseaedf5bd2007-07-24 07:20:09 +020050 mtdcr(uic0pr, 0xFFBFF1EF); /* Adjustment of the polarity */
51 mtdcr(uic0tr, 0x00000900); /* per ref-board manual */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020052 mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
53 mtdcr(uic0sr, 0xffffffff); /* clear all */
54
55 mtdcr(uic1sr, 0xffffffff); /* clear all */
56 mtdcr(uic1er, 0x00000000); /* disable all */
57 mtdcr(uic1cr, 0x00000000); /* all non-critical */
Stefan Roeseaedf5bd2007-07-24 07:20:09 +020058 mtdcr(uic1pr, 0xFFFFC6A5); /* Adjustment of the polarity */
59 mtdcr(uic1tr, 0x60000040); /* per ref-board manual */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020060 mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
61 mtdcr(uic1sr, 0xffffffff); /* clear all */
62
63 mtdcr(uic2sr, 0xffffffff); /* clear all */
64 mtdcr(uic2er, 0x00000000); /* disable all */
65 mtdcr(uic2cr, 0x00000000); /* all non-critical */
66 mtdcr(uic2pr, 0x27C00000); /* Adjustment of the polarity */
Stefan Roeseaedf5bd2007-07-24 07:20:09 +020067 mtdcr(uic2tr, 0x3C000000); /* per ref-board manual */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020068 mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
Stefan Roeseaedf5bd2007-07-24 07:20:09 +020069 mtdcr(uic2sr, 0xffffffff); /* clear all */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020070
71 /* Trace Pins are disabled. SDR0_PFC0 Register */
72 mtsdr(SDR0_PFC0, 0x0);
73
74 /* select Ethernet pins */
75 mfsdr(SDR0_PFC1, sdr0_pfc1);
76 /* SMII via ZMII */
77 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
78 SDR0_PFC1_SELECT_CONFIG_6;
79 mfsdr(SDR0_PFC2, sdr0_pfc2);
80 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
81 SDR0_PFC2_SELECT_CONFIG_6;
82
83 /* enable SPI (SCP) */
84 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
85
86 mtsdr(SDR0_PFC2, sdr0_pfc2);
87 mtsdr(SDR0_PFC1, sdr0_pfc1);
88
89 mtsdr(SDR0_PFC4, 0x80000000);
90
91 /* PCI arbiter disabled */
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020092 /* PCI Host Configuration disbaled */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020093 mfsdr(sdr_pci0, reg);
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020094 reg = 0;
Stefan Roeseb765ffb2007-06-15 08:18:01 +020095 mtsdr(sdr_pci0, 0x00000000 | reg);
96
97 gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
98
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +010099#if CONFIG_POST & CFG_POST_BSPEC1
100 gpio_write_bit(CFG_GPIO_HIGHSIDE, 1);
101
102 reg = 0; /* reuse as counter */
103 out_be32((void *)CFG_DSPIC_TEST_ADDR,
104 in_be32((void *)CFG_DSPIC_TEST_ADDR)
105 & ~CFG_DSPIC_TEST_MASK);
106 while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) {
107 udelay(1000);
108 }
109 gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);
110 if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) {
111 /* set "boot error" flag */
112 out_be32((void *)CFG_DSPIC_TEST_ADDR,
113 in_be32((void *)CFG_DSPIC_TEST_ADDR) |
114 CFG_DSPIC_TEST_MASK);
115 }
116#endif
117
Stefan Roese54fd6c92007-11-13 08:18:20 +0100118 /*
119 * Reset PHY's:
120 * The PHY's need a 2nd reset pulse, since the MDIO address is latched
121 * upon reset, and with the first reset upon powerup, the addresses are
122 * not latched reliable, since the IRQ line is multiplexed with an
123 * MDIO address. A 2nd reset at this time will make sure, that the
124 * correct address is latched.
125 */
126 gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
127 gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
128 udelay(1000);
129 gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
130 gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
131 udelay(1000);
132 gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
133 gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
134
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200135 return 0;
136}
137
138/*---------------------------------------------------------------------------+
139 | misc_init_r.
140 +---------------------------------------------------------------------------*/
141int misc_init_r(void)
142{
143 u32 pbcr;
144 int size_val = 0;
145 u32 reg;
146 unsigned long usb2d0cr = 0;
147 unsigned long usb2phy0cr, usb2h0cr = 0;
148 unsigned long sdr0_pfc1;
149
150 /*
151 * FLASH stuff...
152 */
153
154 /* Re-do sizing to get full correct info */
155
156 /* adjust flash start and offset */
157 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
158 gd->bd->bi_flashoffset = 0;
159
160 mfebc(pb0cr, pbcr);
161 switch (gd->bd->bi_flashsize) {
162 case 1 << 20:
163 size_val = 0;
164 break;
165 case 2 << 20:
166 size_val = 1;
167 break;
168 case 4 << 20:
169 size_val = 2;
170 break;
171 case 8 << 20:
172 size_val = 3;
173 break;
174 case 16 << 20:
175 size_val = 4;
176 break;
177 case 32 << 20:
178 size_val = 5;
179 break;
180 case 64 << 20:
181 size_val = 6;
182 break;
183 case 128 << 20:
184 size_val = 7;
185 break;
186 }
187 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
188 mtebc(pb0cr, pbcr);
189
190 /*
191 * Re-check to get correct base address
192 */
193 flash_get_size(gd->bd->bi_flashstart, 0);
194
195 /* Monitor protection ON by default */
196 (void)flash_protect(FLAG_PROTECT_SET,
197 -CFG_MONITOR_LEN,
198 0xffffffff,
Stefan Roese9f24a802007-07-24 09:52:52 +0200199 &flash_info[1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200200
201 /* Env protection ON by default */
202 (void)flash_protect(FLAG_PROTECT_SET,
203 CFG_ENV_ADDR_REDUND,
204 CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
Stefan Roese9f24a802007-07-24 09:52:52 +0200205 &flash_info[1]);
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200206
207 /*
208 * USB suff...
209 */
210 /* SDR Setting */
211 mfsdr(SDR0_PFC1, sdr0_pfc1);
212 mfsdr(SDR0_USB0, usb2d0cr);
213 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
214 mfsdr(SDR0_USB2H0CR, usb2h0cr);
215
216 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
217 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
218 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
219 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
220 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
221 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
222 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
223 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
224 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
225 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
226
227 /* An 8-bit/60MHz interface is the only possible alternative
228 when connecting the Device to the PHY */
229 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
230 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
231
232 mtsdr(SDR0_PFC1, sdr0_pfc1);
233 mtsdr(SDR0_USB0, usb2d0cr);
234 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
235 mtsdr(SDR0_USB2H0CR, usb2h0cr);
236
237 /*
238 * Clear resets
239 */
240 udelay (1000);
241 mtsdr(SDR0_SRST1, 0x00000000);
242 udelay (1000);
243 mtsdr(SDR0_SRST0, 0x00000000);
244
245 printf("USB: Host(int phy) Device(ext phy)\n");
246
247 /*
248 * Clear PLB4A0_ACR[WRP]
249 * This fix will make the MAL burst disabling patch for the Linux
250 * EMAC driver obsolete.
251 */
252 reg = mfdcr(plb4_acr) & ~PLB4_ACR_WRP;
253 mtdcr(plb4_acr, reg);
254
255 /*
Stefan Roese3ad63872007-08-21 16:27:57 +0200256 * Init matrix keyboard
257 */
258 misc_init_r_kbd();
259
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200260 return 0;
261}
262
263int checkboard(void)
264{
265 char *s = getenv("serial#");
266
267 printf("Board: lwmon5");
268
269 if (s != NULL) {
270 puts(", serial# ");
271 puts(s);
272 }
273 putc('\n');
274
275 return (0);
276}
277
278#if defined(CFG_DRAM_TEST)
279int testdram(void)
280{
281 unsigned long *mem = (unsigned long *)0;
282 const unsigned long kend = (1024 / sizeof(unsigned long));
283 unsigned long k, n;
284
285 mtmsr(0);
286
287 for (k = 0; k < CFG_MBYTES_SDRAM;
288 ++k, mem += (1024 / sizeof(unsigned long))) {
289 if ((k & 1023) == 0) {
290 printf("%3d MB\r", k / 1024);
291 }
292
293 memset(mem, 0xaaaaaaaa, 1024);
294 for (n = 0; n < kend; ++n) {
295 if (mem[n] != 0xaaaaaaaa) {
296 printf("SDRAM test fails at: %08x\n",
297 (uint) & mem[n]);
298 return 1;
299 }
300 }
301
302 memset(mem, 0x55555555, 1024);
303 for (n = 0; n < kend; ++n) {
304 if (mem[n] != 0x55555555) {
305 printf("SDRAM test fails at: %08x\n",
306 (uint) & mem[n]);
307 return 1;
308 }
309 }
310 }
311 printf("SDRAM test passes\n");
312 return 0;
313}
314#endif
315
316/*************************************************************************
317 * pci_pre_init
318 *
319 * This routine is called just prior to registering the hose and gives
320 * the board the opportunity to check things. Returning a value of zero
321 * indicates that things are bad & PCI initialization should be aborted.
322 *
323 * Different boards may wish to customize the pci controller structure
324 * (add regions, override default access routines, etc) or perform
325 * certain pre-initialization actions.
326 *
327 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200328#if defined(CONFIG_PCI)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200329int pci_pre_init(struct pci_controller *hose)
330{
331 unsigned long addr;
332
333 /*-------------------------------------------------------------------------+
334 | Set priority for all PLB3 devices to 0.
335 | Set PLB3 arbiter to fair mode.
336 +-------------------------------------------------------------------------*/
337 mfsdr(sdr_amp1, addr);
338 mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
339 addr = mfdcr(plb3_acr);
340 mtdcr(plb3_acr, addr | 0x80000000);
341
342 /*-------------------------------------------------------------------------+
343 | Set priority for all PLB4 devices to 0.
344 +-------------------------------------------------------------------------*/
345 mfsdr(sdr_amp0, addr);
346 mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
347 addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
348 mtdcr(plb4_acr, addr);
349
350 /*-------------------------------------------------------------------------+
351 | Set Nebula PLB4 arbiter to fair mode.
352 +-------------------------------------------------------------------------*/
353 /* Segment0 */
354 addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
355 addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
356 addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
357 addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
358 mtdcr(plb0_acr, addr);
359
360 /* Segment1 */
361 addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
362 addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
363 addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
364 addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
365 mtdcr(plb1_acr, addr);
366
367 return 1;
368}
Stefan Roese466fff12007-06-25 15:57:39 +0200369#endif /* defined(CONFIG_PCI) */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200370
371/*************************************************************************
372 * pci_target_init
373 *
374 * The bootstrap configuration provides default settings for the pci
375 * inbound map (PIM). But the bootstrap config choices are limited and
376 * may not be sufficient for a given board.
377 *
378 ************************************************************************/
379#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
380void pci_target_init(struct pci_controller *hose)
381{
382 /*--------------------------------------------------------------------------+
383 * Set up Direct MMIO registers
384 *--------------------------------------------------------------------------*/
385 /*--------------------------------------------------------------------------+
386 | PowerPC440EPX PCI Master configuration.
387 | Map one 1Gig range of PLB/processor addresses to PCI memory space.
388 | PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
389 | Use byte reversed out routines to handle endianess.
390 | Make this region non-prefetchable.
391 +--------------------------------------------------------------------------*/
392 out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
393 out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
394 out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
395 out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
396 out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
397
398 out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
399 out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
400 out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
401 out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
402 out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
403
404 out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
405 out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
406 out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
407 out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
408
409 /*--------------------------------------------------------------------------+
410 * Set up Configuration registers
411 *--------------------------------------------------------------------------*/
412
413 /* Program the board's subsystem id/vendor id */
414 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
415 CFG_PCI_SUBSYS_VENDORID);
416 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
417
418 /* Configure command register as bus master */
419 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
420
421 /* 240nS PCI clock */
422 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
423
424 /* No error reporting */
425 pci_write_config_word(0, PCI_ERREN, 0);
426
427 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
428
429}
430#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
431
432/*************************************************************************
433 * pci_master_init
434 *
435 ************************************************************************/
436#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
437void pci_master_init(struct pci_controller *hose)
438{
439 unsigned short temp_short;
440
441 /*--------------------------------------------------------------------------+
442 | Write the PowerPC440 EP PCI Configuration regs.
443 | Enable PowerPC440 EP to be a master on the PCI bus (PMM).
444 | Enable PowerPC440 EP to act as a PCI memory target (PTM).
445 +--------------------------------------------------------------------------*/
446 pci_read_config_word(0, PCI_COMMAND, &temp_short);
447 pci_write_config_word(0, PCI_COMMAND,
448 temp_short | PCI_COMMAND_MASTER |
449 PCI_COMMAND_MEMORY);
450}
451#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
452
453/*************************************************************************
454 * is_pci_host
455 *
456 * This routine is called to determine if a pci scan should be
457 * performed. With various hardware environments (especially cPCI and
458 * PPMC) it's insufficient to depend on the state of the arbiter enable
459 * bit in the strap register, or generic host/adapter assumptions.
460 *
461 * Rather than hard-code a bad assumption in the general 440 code, the
462 * 440 pci code requires the board to decide at runtime.
463 *
464 * Return 0 for adapter mode, non-zero for host (monarch) mode.
465 *
466 *
467 ************************************************************************/
468#if defined(CONFIG_PCI)
469int is_pci_host(struct pci_controller *hose)
470{
471 /* Cactus is always configured as host. */
472 return (1);
473}
474#endif /* defined(CONFIG_PCI) */
475
476void hw_watchdog_reset(void)
477{
478 int val;
479
480 /*
481 * Toggle watchdog output
482 */
483 val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
484 gpio_write_bit(CFG_GPIO_WATCHDOG, val);
485}
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200486
487int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
488{
489 if (argc < 2) {
490 printf("Usage:\n%s\n", cmdtp->usage);
491 return 1;
492 }
493
494 if ((strcmp(argv[1], "on") == 0)) {
495 gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1);
496 } else if ((strcmp(argv[1], "off") == 0)) {
497 gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0);
498 } else {
499 printf("Usage:\n%s\n", cmdtp->usage);
500 return 1;
501 }
502
503
504 return 0;
505}
506
507U_BOOT_CMD(
508 eepromwp, 2, 0, do_eeprom_wp,
509 "eepromwp- eeprom write protect off/on\n",
510 "<on|off> - enable (on) or disable (off) I2C EEPROM write protect\n"
511);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100512
513#if defined(CONFIG_VIDEO)
514#include <video_fb.h>
515#include <mb862xx.h>
516
517extern GraphicDevice mb862xx;
518
519static const gdc_regs init_regs [] =
520{
521 {0x0100, 0x00000f00},
522 {0x0020, 0x801401df},
523 {0x0024, 0x00000000},
524 {0x0028, 0x00000000},
525 {0x002c, 0x00000000},
526 {0x0110, 0x00000000},
527 {0x0114, 0x00000000},
528 {0x0118, 0x01df0280},
529 {0x0004, 0x031f0000},
530 {0x0008, 0x027f027f},
531 {0x000c, 0x015f028f},
532 {0x0010, 0x020c0000},
533 {0x0014, 0x01df01ea},
534 {0x0018, 0x00000000},
535 {0x001c, 0x01e00280},
536 {0x0100, 0x80010f00},
537 {0x0, 0x0}
538};
539
540const gdc_regs *board_get_regs (void)
541{
542 return init_regs;
543}
544
545/* Returns Lime base address */
546unsigned int board_video_init (void)
547{
548 /*
549 * Reset Lime controller
550 */
551 gpio_write_bit(CFG_GPIO_LIME_S, 1);
552 udelay(500);
553 gpio_write_bit(CFG_GPIO_LIME_RST, 1);
554
555 /* Lime memory clock adjusted to 100MHz */
556 out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
557 /* Wait untill time expired. Because of requirements in lime manual */
558 udelay(300);
559 /* Write lime controller memory parameters */
560 out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
561
562 mb862xx.winSizeX = 640;
563 mb862xx.winSizeY = 480;
564 mb862xx.gdfBytesPP = 2;
565 mb862xx.gdfIndex = GDF_15BIT_555RGB;
566
567 return CFG_LIME_BASE_0;
568}
569
Yuri Tikhonov46bc0a92008-03-18 13:27:57 +0100570#define DEFAULT_BRIGHTNESS 0x64
571
572static void board_backlight_brightness(int brightness)
Anatolij Gustschind610a602008-01-11 15:31:09 +0100573{
Yuri Tikhonov46bc0a92008-03-18 13:27:57 +0100574 if (brightness > 0) {
Anatolij Gustschind610a602008-01-11 15:31:09 +0100575 /* pwm duty, lamp on */
Yuri Tikhonov46bc0a92008-03-18 13:27:57 +0100576 out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness);
Anatolij Gustschind610a602008-01-11 15:31:09 +0100577 out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701);
578 } else {
579 /* lamp off */
580 out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00);
581 out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00);
582 }
583}
584
Yuri Tikhonov46bc0a92008-03-18 13:27:57 +0100585void board_backlight_switch (int flag)
586{
587 char * param;
588 int rc;
589
590 if (flag) {
591 param = getenv("brightness");
592 rc = param ? simple_strtol(param, NULL, 10) : -1;
593 if (rc < 0)
594 rc = DEFAULT_BRIGHTNESS;
595 } else {
596 rc = 0;
597 }
598 board_backlight_brightness(rc);
599}
600
Anatolij Gustschind610a602008-01-11 15:31:09 +0100601#if defined(CONFIG_CONSOLE_EXTRA_INFO)
602/*
603 * Return text to be printed besides the logo.
604 */
605void video_get_info_str (int line_number, char *info)
606{
607 if (line_number == 1) {
608 strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
609 } else {
610 info [0] = '\0';
611 }
612}
613#endif
614#endif /* CONFIG_VIDEO */
Yuri Tikhonov0f009f72008-02-04 17:11:53 +0100615
616void board_reset(void)
617{
618 gpio_write_bit(CFG_GPIO_BOARD_RESET, 1);
619}