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Bo Shen3225f342013-05-12 22:40:54 +00001/*
2 * Configuation settings for the SAMA5D3xEK board.
3 *
4 * Copyright (C) 2012 - 2013 Atmel
5 *
6 * based on at91sam9m10g45ek.h by:
7 * Stelian Pop <stelian@popies.net>
8 * Lead Tech Design <www.leadtechdesign.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Bo Shen3225f342013-05-12 22:40:54 +000011 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#include <asm/hardware.h>
17
18#define CONFIG_SYS_TEXT_BASE 0x26f00000
19
20/* ARM asynchronous clock */
21#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
22#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Bo Shen3225f342013-05-12 22:40:54 +000023
Bo Shen3225f342013-05-12 22:40:54 +000024#define CONFIG_ARCH_CPU_INIT
25
Bo Shenc5e88852013-11-15 11:12:38 +080026#ifndef CONFIG_SPL_BUILD
Bo Shen3225f342013-05-12 22:40:54 +000027#define CONFIG_SKIP_LOWLEVEL_INIT
Bo Shenc5e88852013-11-15 11:12:38 +080028#endif
29
Bo Shen3225f342013-05-12 22:40:54 +000030#define CONFIG_BOARD_EARLY_INIT_F
31#define CONFIG_DISPLAY_CPUINFO
32
33#define CONFIG_CMD_BOOTZ
34#define CONFIG_OF_LIBFDT /* Device Tree support */
35
Bo Shen525049d2014-04-24 11:42:13 +080036#define CONFIG_SYS_GENERIC_BOARD
37
Bo Shen3225f342013-05-12 22:40:54 +000038/* general purpose I/O */
39#define CONFIG_AT91_GPIO
40
41/* serial console */
42#define CONFIG_ATMEL_USART
43#define CONFIG_USART_BASE ATMEL_BASE_DBGU
44#define CONFIG_USART_ID ATMEL_ID_DBGU
45
46/*
47 * This needs to be defined for the OHCI code to work but it is defined as
48 * ATMEL_ID_UHPHS in the CPU specific header files.
49 */
50#define ATMEL_ID_UHP ATMEL_ID_UHPHS
51
52/*
53 * Specify the clock enable bit in the PMC_SCER register.
54 */
55#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
56
57/* LCD */
58#define CONFIG_LCD
59#define LCD_BPP LCD_COLOR16
60#define LCD_OUTPUT_BPP 24
61#define CONFIG_LCD_LOGO
Bo Shen3225f342013-05-12 22:40:54 +000062#define CONFIG_LCD_INFO
63#define CONFIG_LCD_INFO_BELOW_LOGO
64#define CONFIG_SYS_WHITE_ON_BLACK
65#define CONFIG_ATMEL_HLCD
66#define CONFIG_ATMEL_LCD_RGB565
67#define CONFIG_SYS_CONSOLE_IS_IN_ENV
68
69/* board specific (not enough SRAM) */
70#define CONFIG_SAMA5D3_LCD_BASE 0x23E00000
71
72#define CONFIG_BOOTDELAY 3
73
74/*
75 * BOOTP options
76 */
77#define CONFIG_BOOTP_BOOTFILESIZE
78#define CONFIG_BOOTP_BOOTPATH
79#define CONFIG_BOOTP_GATEWAY
80#define CONFIG_BOOTP_HOSTNAME
81
Bo Shend6b79432014-07-18 16:43:08 +080082/* NOR flash */
83#define CONFIG_CMD_FLASH
84
85#ifdef CONFIG_CMD_FLASH
86#define CONFIG_FLASH_CFI_DRIVER
87#define CONFIG_SYS_FLASH_CFI
88#define CONFIG_SYS_FLASH_PROTECTION
89#define CONFIG_SYS_FLASH_BASE 0x10000000
90#define CONFIG_SYS_MAX_FLASH_SECT 131
91#define CONFIG_SYS_MAX_FLASH_BANKS 1
92#else
Bo Shen3225f342013-05-12 22:40:54 +000093#define CONFIG_SYS_NO_FLASH
Bo Shend6b79432014-07-18 16:43:08 +080094#endif
Bo Shen3225f342013-05-12 22:40:54 +000095
96/*
97 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100#undef CONFIG_CMD_FPGA
101#undef CONFIG_CMD_IMI
102#undef CONFIG_CMD_LOADS
103#define CONFIG_CMD_PING
104#define CONFIG_CMD_DHCP
105
106/* SDRAM */
107#define CONFIG_NR_DRAM_BANKS 1
108#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS
109#define CONFIG_SYS_SDRAM_SIZE 0x20000000
110
Bo Shenc5e88852013-11-15 11:12:38 +0800111#ifdef CONFIG_SPL_BUILD
112#define CONFIG_SYS_INIT_SP_ADDR 0x310000
113#else
Bo Shen3225f342013-05-12 22:40:54 +0000114#define CONFIG_SYS_INIT_SP_ADDR \
115 (CONFIG_SYS_SDRAM_BASE + 4 * 1024 - GENERATED_GBL_DATA_SIZE)
Bo Shenc5e88852013-11-15 11:12:38 +0800116#endif
Bo Shen3225f342013-05-12 22:40:54 +0000117
118/* SerialFlash */
119#define CONFIG_CMD_SF
120
121#ifdef CONFIG_CMD_SF
122#define CONFIG_ATMEL_SPI
123#define CONFIG_SPI_FLASH
124#define CONFIG_SPI_FLASH_ATMEL
125#define CONFIG_SF_DEFAULT_SPEED 30000000
126#endif
127
128/* NAND flash */
129#define CONFIG_CMD_NAND
130
131#ifdef CONFIG_CMD_NAND
Bo Shen3225f342013-05-12 22:40:54 +0000132#define CONFIG_NAND_ATMEL
133#define CONFIG_SYS_MAX_NAND_DEVICE 1
134#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
135/* our ALE is AD21 */
136#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
137/* our CLE is AD22 */
138#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
139#define CONFIG_SYS_NAND_ONFI_DETECTION
140/* PMECC & PMERRLOC */
141#define CONFIG_ATMEL_NAND_HWECC
142#define CONFIG_ATMEL_NAND_HW_PMECC
143#define CONFIG_PMECC_CAP 4
144#define CONFIG_PMECC_SECTOR_SIZE 512
Bo Shen3225f342013-05-12 22:40:54 +0000145#define CONFIG_CMD_NAND_TRIMFFS
146#endif
147
148/* Ethernet Hardware */
149#define CONFIG_MACB
150#define CONFIG_RMII
Bo Shen3225f342013-05-12 22:40:54 +0000151#define CONFIG_NET_RETRY_COUNT 20
152#define CONFIG_MACB_SEARCH_PHY
Bo Shene08d6f32013-06-26 10:11:06 +0800153#define CONFIG_RGMII
154#define CONFIG_CMD_MII
155#define CONFIG_PHYLIB
156#define CONFIG_PHY_MICREL
157#define CONFIG_PHY_MICREL_KSZ9021
Bo Shen3225f342013-05-12 22:40:54 +0000158
159/* MMC */
160#define CONFIG_CMD_MMC
161
162#ifdef CONFIG_CMD_MMC
163#define CONFIG_MMC
164#define CONFIG_GENERIC_MMC
165#define CONFIG_GENERIC_ATMEL_MCI
166#define ATMEL_BASE_MMCI ATMEL_BASE_MCI0
167#endif
168
169/* USB */
170#define CONFIG_CMD_USB
171
172#ifdef CONFIG_CMD_USB
173#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +0800174#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Bo Shen3225f342013-05-12 22:40:54 +0000175#define CONFIG_USB_OHCI_NEW
176#define CONFIG_SYS_USB_OHCI_CPU_INIT
177#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI
178#define CONFIG_SYS_USB_OHCI_SLOT_NAME "sama5d3"
179#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3
180#define CONFIG_DOS_PARTITION
181#define CONFIG_USB_STORAGE
182#endif
183
Bo Shen3668ce32013-09-11 18:24:51 +0800184/* USB device */
185#define CONFIG_USB_GADGET
186#define CONFIG_USB_GADGET_DUALSPEED
187#define CONFIG_USB_GADGET_ATMEL_USBA
188#define CONFIG_USB_ETHER
189#define CONFIG_USB_ETH_RNDIS
190#define CONFIG_USBNET_MANUFACTURER "Atmel SAMA5D3xEK"
191
Bo Shen3225f342013-05-12 22:40:54 +0000192#if defined(CONFIG_CMD_USB) || defined(CONFIG_CMD_MMC)
193#define CONFIG_CMD_FAT
194#endif
195
196#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
197
198#ifdef CONFIG_SYS_USE_SERIALFLASH
199/* bootstrap + u-boot + env + linux in serial flash */
200#define CONFIG_ENV_IS_IN_SPI_FLASH
201#define CONFIG_ENV_OFFSET 0x5000
202#define CONFIG_ENV_SIZE 0x3000
203#define CONFIG_ENV_SECT_SIZE 0x1000
204#define CONFIG_BOOTCOMMAND "sf probe 0; " \
205 "sf read 0x22000000 0x42000 0x300000; " \
206 "bootm 0x22000000"
207#elif CONFIG_SYS_USE_NANDFLASH
208/* bootstrap + u-boot + env in nandflash */
209#define CONFIG_ENV_IS_IN_NAND
210#define CONFIG_ENV_OFFSET 0xc0000
211#define CONFIG_ENV_OFFSET_REDUND 0x100000
212#define CONFIG_ENV_SIZE 0x20000
213#define CONFIG_BOOTCOMMAND "nand read 0x21000000 0x180000 0x80000;" \
214 "nand read 0x22000000 0x200000 0x600000;" \
215 "bootm 0x22000000 - 0x21000000"
216#elif CONFIG_SYS_USE_MMC
217/* bootstrap + u-boot + env in sd card */
218#define CONFIG_ENV_IS_IN_MMC
219#define CONFIG_ENV_OFFSET 0x2000
220#define CONFIG_ENV_SIZE 0x1000
221#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x21000000 dtb; " \
222 "fatload mmc 0:1 0x22000000 uImage; " \
223 "bootm 0x22000000 - 0x21000000"
224#define CONFIG_SYS_MMC_ENV_DEV 0
225#else
Bo Shena4c79b32013-08-11 14:26:20 +0000226#define CONFIG_ENV_IS_NOWHERE
Bo Shen3225f342013-05-12 22:40:54 +0000227#endif
228
229#ifdef CONFIG_SYS_USE_MMC
230#define CONFIG_BOOTARGS \
231 "console=ttyS0,115200 earlyprintk " \
232 "root=/dev/mmcblk0p2 rw rootwait"
233#else
234#define CONFIG_BOOTARGS \
235 "console=ttyS0,115200 earlyprintk " \
236 "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \
237 "256K(env),256k(evn_redundent),256k(spare)," \
238 "512k(dtb),6M(kernel)ro,-(rootfs) " \
239 "rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs"
240#endif
241
242#define CONFIG_BAUDRATE 115200
243
244#define CONFIG_SYS_PROMPT "U-Boot> "
245#define CONFIG_SYS_CBSIZE 256
246#define CONFIG_SYS_MAXARGS 16
247#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
248 sizeof(CONFIG_SYS_PROMPT) + 16)
249#define CONFIG_SYS_LONGHELP
250#define CONFIG_CMDLINE_EDITING
251#define CONFIG_AUTO_COMPLETE
252#define CONFIG_SYS_HUSH_PARSER
253
254/* Size of malloc() pool */
255#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
256
Bo Shenc5e88852013-11-15 11:12:38 +0800257/* SPL */
Bo Shenc5e88852013-11-15 11:12:38 +0800258#define CONFIG_SPL_FRAMEWORK
259#define CONFIG_SPL_TEXT_BASE 0x300000
260#define CONFIG_SPL_MAX_SIZE 0x10000
261#define CONFIG_SPL_BSS_START_ADDR 0x20000000
262#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
263#define CONFIG_SYS_SPL_MALLOC_START 0x20080000
264#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000
265
266#define CONFIG_SPL_LIBCOMMON_SUPPORT
267#define CONFIG_SPL_LIBGENERIC_SUPPORT
268#define CONFIG_SPL_GPIO_SUPPORT
269#define CONFIG_SPL_SERIAL_SUPPORT
270
271#define CONFIG_SPL_BOARD_INIT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800272#define CONFIG_SYS_MONITOR_LEN (512 << 10)
273
Bo Shenc5e88852013-11-15 11:12:38 +0800274#ifdef CONFIG_SYS_USE_MMC
275#define CONFIG_SPL_LDSCRIPT arch/arm/cpu/at91-common/u-boot-spl.lds
276#define CONFIG_SPL_MMC_SUPPORT
277#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
278#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x200
Guillaume GARDET205b4f32014-10-15 17:53:11 +0200279#define CONFIG_SYS_MMC_SD_FS_BOOT_PARTITION 1
280#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shenc5e88852013-11-15 11:12:38 +0800281#define CONFIG_SPL_FAT_SUPPORT
282#define CONFIG_SPL_LIBDISK_SUPPORT
Bo Shen8a45b0b2014-03-03 14:47:15 +0800283
Bo Shen27019e42014-03-03 14:47:17 +0800284#elif CONFIG_SYS_USE_NANDFLASH
285#define CONFIG_SPL_NAND_SUPPORT
286#define CONFIG_SPL_NAND_DRIVERS
287#define CONFIG_SPL_NAND_BASE
288#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
289#define CONFIG_SYS_NAND_5_ADDR_CYCLE
290#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
291#define CONFIG_SYS_NAND_PAGE_COUNT 64
292#define CONFIG_SYS_NAND_OOBSIZE 64
293#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
294#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0
Andreas Bießmanne166a832014-05-19 14:23:41 +0200295#define CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER
Bo Shen27019e42014-03-03 14:47:17 +0800296
Bo Shen8a45b0b2014-03-03 14:47:15 +0800297#elif CONFIG_SYS_USE_SERIALFLASH
298#define CONFIG_SPL_SPI_SUPPORT
299#define CONFIG_SPL_SPI_FLASH_SUPPORT
300#define CONFIG_SPL_SPI_LOAD
Bo Shen8a45b0b2014-03-03 14:47:15 +0800301#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400
302
Bo Shenc5e88852013-11-15 11:12:38 +0800303#endif
304
Bo Shen3225f342013-05-12 22:40:54 +0000305#endif